搜索资源列表
cascaded_adder
- implementation of cascade adder with verilog plus testbench
contador_n_bits
- n-bits counter vhdl with testbench. contador de nbits en vhdl con simulacion.
BMD.RAR
- xilinx BMD ver 10 pciexpress testbench for master design
ascfifotestbench
- 自写异步 fifo TESTBench 该fifo对初学者很有帮助！-Since the write fifo TESTBench asynchronous fifo very helpful for beginners!
rom_table
- rom vector table vhdl and Testbench
asynfifo
- 异步fifo，用Verilog编写，包含testbench，已经通过调试，需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
Modelsim_fredevider_testbench_TEXTIO
- 此文档通过分频器的例子描述了如何使用modelsim，如何编写testbench以及textio的使用-This document is an example through the divider describes how to use the modelsim, how to write a testbench and use textio
ModelSimweisijiaocheng
- modelsim 使用流程，一个记数仿真器详细设计步骤， FORCE和RUN两个命令解释，TestBench的一个例子。-modelsim using the process, a detailed design of the emulator counting steps, FORCE, and RUN 2 command interpreter, TestBench an example.
Springer_2006_SystemVerilog_for_Verificatio_Chris
- A Guide to Learning the Testbench System Verilog Language Features
UART
- 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
Desktop
- 四选一多路选择器 modelsim testbench-Select more than one four-way selector modelsim testbench
fifo64x8_tb
- Testbench for Xilinx 64x8 FIFO.
verilog_example
- 九个verilog源码例子，包括寄存器，状态机等，含testbench-9 verilog source code examples, including registers, state machines, with testbench
test_bech
- verilog + testbench 文件的读写操作-verilog+ testbench
interleaver
- 交织编码器的verilog代码实现，此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
sdram_ctrl
- sdram 控制器 含testbench-sdram controller with testbench
src
- FIR滤波器的设计，完整包括RTL代码、testbench等，清晰易懂。-FIR filter design, complete coverage of RTL code, testbench, etc., clear and understandable.
Testbench(Verilog)
- verilog验证平台的使用 很不错 很详细 想具体-verilog verification platform is more like using a very good specific
Spartan3E-LCD
- 一个基于Spartan3E板子的LCD接受的代码附带testbench-A board of LCD-based Spartan3E accepted code with testbench
verilog_testbench_genetator
- 这是一个perl程序 只需要在cmd中运行，参数为你的Verilog名字 功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010---------------