搜索资源列表
TestBench
- TestBench for stop_watch in VHDL
TestBench_Primer
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-Writing testbench
FifoAndTestbench
- 这是一个verilog编写的同步fifo和testbench的设计-It is a synchronous fifo and testbench design with verilog
DualPortRam
- VHDL Dpram including clock divider, D4to7, Scan4Digit and of course TOP level as well as testbench info
FIR_CODE
- 4-taps FIR VHDL code with testbench
fifo_tb
- verilog implementation of 16X4 fifo with testbench
get-start-with-modulesim
- 内含基于altera公司的FPGA芯片用modulesim仿真步骤，和详细实例，教会怎么使用modulesim仿真和编写testbench程序。-Altera FPGA-based embedded chip company with modulesim simulation steps, and detailed examples, how to use the church modulesim testbench simulation and preparation procedures.
testbench
- 一个简单的testbench示例，显示基本用法-testbench examples
high-efficiency-testbench
- 用VHDL编写高效率testbench 中文-Efficient testbench written in VHDL Chinese
A-Verilog-HDL-Test-Bench-Primer
- verilog testbench 编写入门，轻松教会编写测试代码-shell interpreter tutorial information, content, round and rich, from the basics
Verilog-testbench
- 北大数字集成电路课件--15_Verilog-testbench的写法.ppt-Verilog-testbench .ppt
how-to-write-testbench
- 怎样写testbench ， 仿真， modelsim， system verilog or verilog， 代码风格，行为级代码-how write testbench，do simulation, modelsim, system verilog or verilog , behaveral level code
verilog-testbench-preliminary
- 本文简单介绍了逻辑验证的入门知识—如何编写TESTBENCH进行逻辑测试-This paper briefly introduces the logic verification started- how to write TESTBENCH logic test
testbench
- 英文文章：testbench入门文档（xilinx的）,ise开发软件-introduce of testbench
how-to-write-testbench
- 如何写好testbench,针对verilog语言-how to write testbench，aimed to verilog
verilog-testbench--technique
- verilog testbench的写法和技巧，适合初学者-Verilog testbench of writing and techniques for beginners
testbench-from-perl
- 直接生成testbench的perl脚本-The software can produce test bench directly by perl
testbench
- VHDL和verilog的TESTBENCH 编写方法。非常好的资料。英文的,但很简单。-Written in VHDL-TESTBENCH. Very good information. In English, but very simple.
VHDL--TESTBENCH
- VHDL描述的TESTBENCH写法 ,对新人有帮助。-The use of VHDL to write TESTBENCH files.useful for new people
testbench(xilinx)
- Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计-The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the wa