搜索资源列表
pwm_higt
- modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program
8051-core
- 8051单片机是一种应用最广泛的单片机.它的内核设计非常精简,这是用Verilog硬件描述语言写的8051单片机内核-8051 is a most widely used SCM. Its kernel design has been streamlined, This is used Verilog hardware descr iption language to write the 8051 microcontroller core
CpldandEepromI2c
- verilog 编写的I2c协议程序，用于cpld读写EEPROM-verilog I2c agreement prepared by the procedures for cpld writable EEPROM
div5
- 简单的VERILOG五分频电路描述，可综合。已经过检验-simple verilog 0.2-frequency circuit descr iption can be integrated. Have been tested
TLC5510APhase
- 运用TLC5510A高速(20M),扫描出波形,测量相位差,两个TLC5510A测两个波形. -TLC5510A use of high-speed (20M), scanning waveform, phase difference measurement, Measuring 2 2 TLC5510A waveform.
rtl_DRAM
- 本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.-program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.
usb_phy
- umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
usb1_funct
- usb1.1的verilog源代码。以及其测试仿真文件，现在很难找其测试文件既testbench-usb1.1 verilog the source code. Simulation and test document, and now it is very difficult to find the paper test testbench
16bit_booth_multiplier_STG
- verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-mo
dirital_clock_7
- verilog实现电子时钟模块，输入60Hz时钟信号和复位，输出时分秒，共6位，每位7段输出用于驱动-verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output
dff_UDP
- verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过-verilog achieve, UDP asynchronous reset with a descr iption of the fringe is triggered D flip-flop, test test pass
fifo_datapath
- verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
I2C_verilog
- I2C总线verilog实现源码，可以完整实现I2C bus的基本功能-I2C Bus verilog achieving source, I2C bus integrity of the basic functions
led_decode
- 用veilog HDL编的七段译码显示电路。自己做的第一个此类程序，编译仿真通过，感觉不错-veilog HDL series with paragraph 107 of the decoder show circuit. I have done the first such procedure, compile through simulation, feeling good
count_usebasketball
- 一个小程序，用Veilog HDL编写的，可以用于篮球比赛的倒计时牌，已在max-plusII上仿真通过。-a small program, prepared by the Veilog HDL, can be used for the basketball game countdown. have max-plusII on through simulation.
risc_spm
- advanced digital design with the verilog hdl-advanced digital design with the verilog h dl
add_16_pipe
- 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Viterbi_v
- Viterbi算法的Verilog源代码。-Viterbi Algorithm Verilog source code.
SPI_Core.ZIP
- SPI协议的VHDL/Verilog语言实现。-SPI agreement VHDL / Verilog language.
i2c_7111_7128
- vhdl,用i2c控制philips的7111和7128-vhdl, and the i2c control philips 7111 and 7128