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adder16bit
- 16位高速加法器，采用verilog语言编写，已经成功仿真，能够运行
VSR4_3
- 甚短距离互联（Veryshort reach VSR）协议编成实现-very short distance from the Internet (Veryshort reach VSR) composition to achieve agreement
asi
- 在公司做的一个用FPGA实现的数字电视系统中 ASI转TS流的程序-done in the company of an FPGA using the digital television system to ASI TS flow procedures
counter_7seg
- 带分频器的bcd计数电路设计，verilog源码-dividers with the bcd count circuit design, Verilog source
Arbiter
- Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
pipemult
- 该源码实现了一个8*8位的乘法器，在实现的过程中用到了宏单元-the source to achieve an 8 * 8 Multiplier that in the process modules used Acer
Xilinx
- Xinx ISE 官方源代码盘第二章-Xinx ISE official source was the second chapter
Xilinx_3
- Xilinx ISE 官方源代码盘 第五章-Xilinx ISE official source was the fifth chapter
Xilinx7-2
- Xilinx ISE 官方源代码盘第七章 Part 2 -Xilinx ISE official source disk Chapter VII Part 2
Xilinx_9
- Xilinx ISE 官方源代码盘第九章-Xilinx ISE official source was the ninth chapter
ASCI_TRAFFIC_LIGHT
- 用VERLOG实现交通灯程序，有红绿两种灯，绿灯到红灯，路灯闪10秒，可以调整红绿灯持续时间-VERLOG achieve with traffic lights procedures, two black lights, the green light to red lights, flashing lights for 10 seconds, can be adjusted duration of traffic lights
lpt03
- 这也是8255的设计,不知道是否好使,希望得到验证-This is 8255 in the design, so I do not know whether the hope of gaining certification
verilog_code_673
- 各种基本单元的verilog模块.对初学者很有帮助的.-basic unit of Verilog modules. Helpful for beginners.
qdesigns
- 关于Altera公司FPGA编程的一些常用实例代码.-on Altera FPGA programming examples of some commonly used code.
userbscan
- xilinx FPGA上使用jtag接口作为用户IO的源码。支持任意位宽度。-Xilinx FPGAs use JTAG interface as user IO source. Support for arbitrary bit width.
xiaolizi1588
- ic读卡器 能读ic电话卡并按时记费-ic reader can read ic phone cards and charged fees on time. .
washmachine
- 在MAXPULS II环境下，采用Verilog开发的自动洗衣机的控制程序,在MAXPULS下可以直接通过编译-in MAXPULS II environment, using Verilog development of the automatic washing machine control procedures, the MAXPULS can be directly through the compiler
7seg_led
- 使用xilinx公司的FPGA实现了七段码的定时器时钟程序-use of the Xilinx FPGA in paragraph 107 of the Code timer clock procedures
dcm
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
ddr
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !