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codestream
- 设计一个模块，从一个窜行数据流里检测出码流“11100”，这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
virtex5
- Virtex® -5 devices are configured by loading application-specific configuration data—the bitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is l
WATERMARKING_FPGA_BITSTREAM_FOR_IP_PROTECTION
- WATERMARKING FPGA BITSTREAM FOR IP PROTECTION
FPGA-Design-Security-Solution
- This document provides a solution to prevent the FPGA designs from being copied. It allows the FPGA design to remain secure even if the configuration bitstream is captured
sigmaDeltaMM
- Sigma Delta Domain Processing. Bitstream processing.-Sigma Delta Domain Processing. Bitstream processing.
DE2_SD_Card_Audio
- 使用Quartus Ⅱ与 NIOS Ⅱ IDE。 功能要求：（可实现某几项或全部） 1. 支持SD卡文件读取； 2. 支持WAV或MP3或其他格式音频，如为压缩格式则需解压缩； 3. 歌曲名称LCD显示； 4. 支持“播放/暂停”控制功能； 5. 支持“前一首”功能； 6. 支持“下一首”功能； 7. 支持LED灯显示音量功能； 8. 支持复位功能； 9. 支持硬启动，FPGA码流文件和软件二进制文件写入ROM，从ROM启动； 10. 支持总歌曲数和第
pulseoximiter1
- 根据血液对光的吸收程度，通过感光器来收集数据，来测试心跳。 TSL235 感光器，放在手指下面，手指上面用光照，从而收集数据。需要配合配件TSL235 感光器，电路板，电阻。-You are going to interface a TSL235 to the FPGA. The TSL235 is a light-to-frequency converter whose output digital bitstream frequency is directly proportional
USRP-PID-Controller-clean
- PID feedback controller project for USRP1 boards (FPGA with a convenient analog front manufactured by ettus research). Implements a bitstream as well as python-based user interface.
OpenBTS-USRP1
- 用于OpenBTS USRP1 Cyclone FPGA比特流的Altera Quartus项目-Altera Quartus Project for OpenBTS USRP1 Cyclone FPGA bitstream