搜索资源列表
pipeline.rar
- 关于FPGA设计中的流水线技巧的使用和例子，一个很好的减少硬件消耗的技巧,About FPGA design using pipelining techniques and examples, a good technique to reduce the hardware consumption
float_data_multiple_use_fixed_
- 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！,a program of float multiply, using 3-stage pipeline technology
add.rar
- 流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）,Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
waterline_adder.rar
- 这是一个用Verilog编写的四级流水线加法器,This is a Verilog prepared with four pipeline adder
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
PipeLine.tar Verilog实现MIPS五段流水线
- Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
PIPE_LINING_CPU_TEAM_24
- 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
cordic
- vhdl语言编写的cordic算法，实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
fir_512_378_mux
- 512阶高速FIR成型滤波器，四相位复用，树形加法和多级流水线结构。-512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.
16bit_pipeline
- 16 bit pipeline design by vhdl.
arm7
- ARM7 VERILOG源码，非常精简，3级流水线-ARM7 VERILOG source code, very streamlined, 3-stage pipeline
RISC
- 32 bit RISC Processor with 3 stage pipeline
Cordic123
- for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly-for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly
post_norm_mul
- 符合IEEE754标准的32位浮点流水线乘法器 采用移位相加算法，-32-bit floating point pipeline multiplier on IEEE754 standard
processor
- processor design istruction load pipeline ,hazard
PipelineCPU
- 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
vhdl-pipeline-mips_latest.tar
- pipeline mips in vhdl