搜索资源列表
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
RX
- 1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
test_uart
- uart VHDL code : include tx,rx,parity bit control
quartus
- des algorithm send rx from serial port
xapp460
- xilinx hdmi tx rx verilog code
uart_tx_rx
- 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complet
uart
- uart - veiloghdl rx, tx, baudrate-uart- veiloghdl rx, tx, baudrate
RxTx
- Serial communication - RS232 Tx Rx
LIP1742CORE_sdio_rx_fsm
- Verilog SDIO RX FSM module-Verilog SDIO RX FSM module
UARTRXTX
- MSP430f449的max232的TX与RX问题解决-MSP430f449 the max232' s problem-solving TX and RX
chipscope_Tx-Rx
- chipscope analysis of mini uart module including counter for spartan 3e
uart_top
- UART的verilog代码，tx，rx皆可-Verilog code of UART, tx, rx Jieke
CC2530-UART2TEST
- descr iption：CC2520UART1-TX&RX-RECEIVE AND TRANSIT
rxtx
- 使用Verilog语言实现的rx转tx，下载使用的时候请您关注下你的所选的FPGA的型号-Use Verilog language rx turn tx, download your concern under the model of the selected FPGA
txrx
- 使用Verilog语言实现的tx转rx，下载使用的时候请您关注下你的所选的FPGA的型号-Use Verilog language tx turn rx, download your concern under the model of the selected FPGA
uart_rx.fit
- uart core : uart rx fit
SERIAL-COMMUNICATION
- RS232 串口通信 2：Rx 3:TX-RS232 serial communication
spi_master
- SPI master code: generates CS and tx/rx data
uart
- Verilog 编写全双工UART input clk, // 这个模块的主时钟 input rst, // 同步复位信号 input rx, // 串口接收端口 output tx, // 串口发射端口 input transmit, // 发送信号 input [7:0] tx_byte, // 发送的字节 output received, // 表明，已接受到一个字节 output [7:0] rx_