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VHDL语言实现的arm内核
- 5个ram核，arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核，verilog写的，有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心，结构良好，简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目，国防科技大学牛人ShengYu Shen写的，原来放在opencores上，
seven
- 这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。-This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full a
polar2rect_VHDL
- 是codic算法实现atan的virilog程序，模块结构如下：Core Structure: sc_corproc.vhd->p2r_cordic.vhd->p2r_cordicpipe.vhd-Atan is the codic algorithm virilog procedures, module is structured as follows: Core Structure: sc_corproc.vhd-> p2r_cordic.vhd-> p2r_cord
iclock
- 基于cycloneII的电子时钟，可实现手动调整时间，良好的人机界面，简单易用，编程结构清晰-CycloneII-based electronic clock, can be manually adjust the time, a good man-machine interface, easy-to-use, structured programming
serial
- 串行转并行的VHDL源代码，结构化编程，学习模块化编程和实用性都很大。-Serial transfer parallel VHDL source code, structured programming, modular programming and practical learning are great.
vhdl2proc
- A structured VHDL design method
keyscan
- verilog语言 4X4键盘扫描 适合于FPGA、verilog语言的初学者 功能模块分块有条理，清晰。帮助初学者掌握FPGA的分层设计-verilog language； 4X4 keyboard scan for FPGA, verilog language modules for beginners ；block structured and clear. Help beginners master the hierarchical FPGA design
count
- VHDl新手入门练习：计数器的实现 结构化练习-VHDl beginners to practice: implementation of a structured exercise counter
Testbench
- 掌握多顶层结构化Testbench的方法-Testbench to know more structured way to the top
Staged-Output-Of-IJVM-By-VHDL
- IJVM by VHDL.IJVM is an instruction set architecture created by Andrew Tanenbaum for his MIC-1 architecture. It is used to teach assembly basics in his book Structured Computer Organization.
hw1
- Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behaves as a 2-bit adder ( X + Y +
A-Structured-VHDL-Design-Method-structdes
- A Structured VHDL Design Method structdes
DC-Adder_Array
- 要求采用快速进位链（Look Ahead）设计一个21位加法器； 2) 采用结构化的设计方法，所有加法器均采用步骤1）的21位加法器； 3) 在加法器阵列中加入流水线结构（Pipelinc），输入连续送数，输出连续出结果，流水线填满后每拍输出一个结果； -1) requires the use of fast carry chain (Look Ahead) design a 21-bit adder 2) the use of structured design metho