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35_486_bus
- 请注意： 本例的源描述包含文件类型，在学习版上不能编译及模拟， 如果您需要对此描述进行编译及模拟，请与北京理工大学 ASIC研究所联系。 另外，此例与第75例是同一个电路的不同部分的描述，可以 一起参考这两个例子的描述。-Please note : The cases include the descr iption of the source file type, version of the study can not be compiled and simulation, if
anjian
- 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) : -- p
ClkScan
- 此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块，一个提供同步信号（H_SYNC和V_SYNC）及像素位置信息；另一个接收像素位置信息，并输出颜色信号。这样便于进行图形修改，同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature
一个8位CISC结构的精简CPU
- 一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
CH2CH1VHDL 数字电路参考书所有程序2
- CH2 VHDL 数字电路参考书所有程序2-CH2 VHDL digital circuit two reference books all procedures
Example-2-2
- 这些是verilog编程实例2,仅供参考-These are two examples of Verilog Programming for reference
8bitsine
- 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
hanming_HDL
- 汉明码编解码的两个例程，作为单元模块分别调入所开发系统-codec of two routines, as modules were transferred by the Development System
ASCI_TRAFFIC_LIGHT
- 用VERLOG实现交通灯程序，有红绿两种灯，绿灯到红灯，路灯闪10秒，可以调整红绿灯持续时间-VERLOG achieve with traffic lights procedures, two black lights, the green light to red lights, flashing lights for 10 seconds, can be adjusted duration of traffic lights
time_display&alarm_clock
- 此为在实验板上通过的时钟闹铃程序，源码分别用ASM和VHDL描叙，但两程序功能不同。-this experiment for the board through the alarm clock procedures were used ASM source VHDL and depicts, but the two procedures different functions.
bicount
- 完整的双向计数器VHDL 程序 大家参考-integrity of the two-way counter VHDL reference procedures
POTS.tar
- Pivoting Object Tracking System - This project implements an object recognition system, where a camera tracks the position of an object. The camera is mounted on an iRobot Create two-wheeled robot, which rotates according to the control signal
A-Two-bits-Counter-Using-VHDL
- 两位VHDL编译计数器的简单实现，并带有异步的复位功能。-A Brief Realization of Two-bits Counter, with an Asynchronous Reset Function
sin-two-90
- 基于FPGA模拟DDS产生两路互为90度得正弦波，以此为依据，可做频率，相位可调的多路波形发生器-FPGA-based simulation DDS generates two sine wave was 90 degrees each other, as a basis to do the frequency, phase adjustable multi-channel waveform generator
Two_Port_RAM
- FPGA libero环境下 介绍ProASIC3/E的TWO Port RAM的使用-FPGA libero circumstances described ProASIC3/E use of TWO Port RAM
TWO-MCU
- 两个SCT80C52单片机之间的通信，包含键盘控制LCD1602显示部分，在实际操作中也成功的经典程序-Two SCT80C52 communication between the microcontroller, a keyboard control LCD1602 display part in practice but also the success of the classic procedure
two-way-counter-design
- 利用FPGA编程-------实现“双向计数器设计”-Use of FPGA programming------- two-way counter design
Two-ways-of-the-pins-of-Quartus-II
- 在Quartus II中分配管脚的两种常用方法.doc 很实用-Two ways of the pins of Quartus II
two-of-the-state-machine-written
- 文档中主要介绍状态机的两种写法--竖着写(在状态中判断事件)和横着写(在事件中判断状态)。-The document introduces two of the state machine written- bristling write (write (in the incident to determine the state judge in the state in the event) and sideways).
two-way-Elevator
- 基于Altera Quartus的双向电梯程序，可以烧制进入Cyclone 的FPGA中进行硬件调试。-Based on the Altera Quartus two-way lift procedures, firing into the Cyclone FPGA hardware debugging.