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一些VHDL源代码
- 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
加法
- 测试向量波形产生：VHDL实例---加法器源程序 -test vector Waveform Generator : VHDL example -- Adder source
ceshixiangliang
- vhdl 测试向量含测试向量（Test Bench）和波形产生：VHDL实例---相应加法器的测试向量（test bench).txt-VHDL test vector containing test vector (Test Bench) and Waveform Generator : VHDL examples --- corresponding Adder test vector (test bench). Txt
QPSK2154
- QPSK的VERLOG源码，在MODELSIM下的一个工程，有测试向量。-QPSK VERLOG source of the MODELSIM of a project, test vector.
csxl
- 相应加法器的测试向量（test bench)-corresponding Adder test vector (test bench )
magnitude
- Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algori
color converter
- The main purpose of the core is a color transform tasks such as CIE XYZRGB, different RGBRGB and RGBYCbCr operations. The main part of color conversions from one to another color system concludes in 3x3 matrix multiplication with vector addition. The
jianbo.rar
- 运用CORDIC算法完成对矢量信号模值及相位信息的运算,The use of CORDIC algorithm for completion of the vector signal value and the phase mode of operation information
AssignmentP3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx
ecp233_1
- elliptic curve processor b-233, include test bench & test vector.
16Point-FFT
- 16点FFT VHDL源程序，The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a
memory_to_vector
- 这是一个Quartus的工程文件和verilog代码，讲如何把memory 变成vector-memory to vector
vector_to_int
- 改程序用VHDL编写 实现由8位二进制数转化成整数的功能-convert vector to int
rom_table
- rom vector table vhdl and Testbench
pwm
- ：随机脉宽调制是解决交流调速系统 中声学噪声的直接有效方法。随机零矢 量分 布是一种很好 的随 机方法，但其不对称的开关函数使其不适用于传统的电流采样方法。通过仿真表明 PWM周期中点采样的方 法无法得到准确的平均值，在分析不对称模式引起的纹波电流对电流平均值影响的基础上，提出了一种适合 于 RZV分布 的电流采样方法 。仿真结果证实该方法简单可行 。 -: Random pulse width modulation speed control system to solve
irq_decoder
- 中断优先编码器的描述，输出中断向量供CPU读取，非常好用，只要稍稍修改，就可以产生您所需要的中断向量。-Descr iption of interrupt priority encoder, the output for the CPU interrupt vector read, very easy to use, if slightly modified, it can generate interrupt vector you need.
square_root
- /* root_x is an 8 bit number with four bits in front of the binary point and four bits behind, increment is an 11 bit number with 3 bits in front of the binary point and 8 bits behind the binary point. In order increase resolution and preve
PERL_PROGRAM
- perl program for generating test vector and veryfying test vector useful for VHDL design verification
hydrophone-and-vector-hydrophon
- 介绍光纤水听器和矢量水听器的原理、性能等，并给出各自的优缺点-Introduce fiber-optic hydrophone and vector hydrophone principle, performance, etc., and give their advantages and disadvantages
Fast Vector Multiplication
- Fast Vector Multiplication in VHDL with carry save adders and final ripple carry adder