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This VHDL code pertains to the DCO model
- code.doc C.1 DCO LEVEL 2 This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between
Digital-FM-transmitter-VHDL-coding
- it is VHDL code for Digital fm modem transmitter block.
DS_FH
- 扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现-Frequency-hopping communication QUARTUS7.0 expanded development environment in the VHDL source code and the achievement of the overall block diagram
dds_test
- 使用图形编辑法（block模式）编写的全套DDS部分，应用于FPGA，开发环境为QuartusII。形象直观，用户可以直接生成代码另行应用-The use of graphic editing method (block mode) part of the preparation of the full range of DDS used in FPGA, the development environment QuartusII. Visual image, the user can be d
stbcmimoofdmnew
- space time block code new
sheji
- 本科毕设，基于cpld的光栅信号处理，包含源代码和模块框图-Undergraduate Bi is located, based on cpld grating signal processing, including source code and block diagram
src
- The source code consist of fft block with integrated on cordic polar to rectangular and rectangular to polar form
VHDL
- 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
FULLTEXT01
- this a program that contains the vhdl m file and vhdl code for the hole block diagram system-this is a program that contains the vhdl m file and vhdl code for the hole block diagram system
LIP6801CORE_audio_block
- Audip Block Verilog sourc code
LIP1215CORE_clkdll
- Clock DLL Block verilog source code
VGA_char_ROM_success
- Verilog HDL语言编写的基于M4K块配置ROM的字符数据存储VGA显示实验代码，引脚分配适用于21EDA的EP2C8Q208开发板, 详细解说请参见特权同学《深入浅出玩转FPGA》视频教程中的《Lesson30：SF-EP1C开发板实验9——基于M4K块配置ROM的字符数据存储VGA显示实验》-experimental code written in Verilog HDL language，ROM configuration based on M4K block for the cha
DSP_h264_VariableBlockSize
- 這是用verilog HDL實現H.264可變block大小的源碼。為了使其能在FPGA上運作，還加入了我自己的改善。-A verilog HDL code for H.264 with variable block size and my own improvement.
adder1
- 此源代码是基于Verilog语言的“与-或-非”门电路 、用 case语句描述的 4 选 1 数据选择器、同步置数、同步清零的计数器 、用 always 过程语句描述的简单算术逻辑单元、用 begin-end 串行块产生信号波形 ，有广泛的应用，比如编码器领域。-This source code is based on the Verilog language, " and- or- not" gate, with the case statement described in
CRCDecoding
- CRC检错程序。只能检错不能纠错。（40,32）的分组码检错，反馈函数：x8+x7+x4+x3+x+1-CRC error detection process. Not only error detection correction. (40,32) and block code error detection, feedback function: x8+ x7+ x4+ x3+ x+1
Block.nonblock
- verilog 中阻塞和非阻塞的电路设计的比较 代码和设计图-Verilog and VHDL block and nonblock design comparison code and layout
Ram-block-code
- It is a VHDL code for Block RAM
code(opp)
- vhdl语言实现线性分组码的编码以及解码-vhdl language of linear block code encoding and decoding
Block-cipher
- block cipher encryption code
RAM_BLOCK
- Ram block code in Verilog