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leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
Micron_SDRAM_DDR2Simulation_mo
- DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme,DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
MySDTEST
- 读取F16文件系统的SD卡里面的bmp文件-To read bmp file of F16 file system on SD card
RISC-CPU
- 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放
MTDB_SYSTEM_CD_V1.0
- ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel Daughter Board (MTDB)）扩展开发包。 里为有两个开源的例子 1.MTDB_SD_Card_Audio,从SD卡中读取WAV文件然后通过DA播放，这个对不SD Card的初学者非常的有用，可以知道使用FPGA SPI来读写SD CARD。 2.MTDB_Systhesiz
all_packages_20080525.tar
- FMF VHDL Models All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We hav
geshihua
- 读取文件的数据,并且按照一定的栏位排序.-Read the data file, and in accordance with a certain sort column.
sdram
- 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程 目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文
fifobaseddprammemory
- This file if about DPram based fifo storage... wirte and read in both ports
test
- 从文件中读取波形文件的testbench例子，大家可以参考-Read from the file testbench waveform file example, we can refer to
Audio_Reader_Flash_DE2
- This an DE2 card software, which is able to read some Audio file from a memory (Flash for example). Extendable to read from a SD card, and to write on it.-This is an DE2 card software, which is able to read some Audio file from a memory (Flash for
cpu86
- CPU86 - Free VHDL CPU8088 IP core Copyright (C) 2005-2010 HT-LAB Quick run: 1) Open a DOSBox/Cygwin shell 2) Navigate to the web_cpu88/Modelsim directory. 3) Execute run.bat See website for more details. The CPU86 cor
verilog_testbench_genetator
- 这是一个perl程序 只需要在cmd中运行，参数为你的Verilog名字 功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010---------------
pskdem_fixed
- psk解调的定点仿真模型。另外DEC2HEX.C负责将十进制的数据文件转换为十六进制的数据文件，因为MATLAB输出数据格式为十进制，而NC-VERILOG能够读取的数据格式为十六进制，所以需要转换。-psk demodulation of the fixed-point simulation models. In addition DEC2HEX.C responsible for the data file is converted to decimal hex data file, as
1602jtxs
- 1602液晶显示器的头文件，主要功能是进行lcd的初始化，及写指令、写数据、检测忙碌状态、读数据、输出字符和字符串子函数程序。主函数中写出显示的光标地址和要显示的字符串就可进行仿真。用于初学lcd的朋友，可进行简单的显示字符串。-1602 LCD header file, the main function is to carry out lcd initialization, and write commands, write data, detect busy state, read dat
nios_de2_70_sdcard_basics
- Basic example to read a TXT file from a SD-Card in the DE2-70 Board.
dpramcore
- 基于altera fpga的dpram ipcore 设计，包含整个工程和modelsim仿真文件。读写地址及读写使能是通过数据产生模块来产生。-Altera fpga dpram ipcore design, including engineering and modelsim simulation file. Read and write address and read and write is through the data module.
register file generation
- the zip file consist of the verilog code which generate the 32 bit reg file so that u can read and write the data into them
textfilereading1
- It is a VHDL code for Text file reading which reads a code for In.txt file and which produces output in out.txt file by IEEE file read and writing lecture.
arm9
- 研究生课程中，ARM9模型简单功能的实现，以及基于文件读入的功能测试。-From graduate courses : ARM9 model, simple function implementation, and functional test based on file-read operation.