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CIC.rar
- cpld/fpga积分梳状滤波器(CIC)设计,cpld/fpga Integral comb filter (CIC) design
BPSK_track_10.23M_BD_IF46.52MHz
- in tracking programm，actualize communications between DSP and FPGA Besides produce ahead code present code late code and correlation integral result-communications between DSP and FPGA Besides produce ahead code present code late code and correlation
VHDL_fre_div
- 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of ex
ccmul
- FFT旋转因子，旋转因子是蝶形运算的组成部分，是数字信号处理FFT算法的基础部分-FFT twiddle factor, rotation factor is an integral part of the butterfly, digital signal processing is a fundamental part of FFT algorithm
232543
- FPGA Implementation of QFT based Controller for a Buck type DC-DC Power Converter and Comparison with Fractional and Integral Order PID Controllers
FPGA-PID-
- FPGA闭环控制电路积分分离式PID算法子程序 算法函数 中断函数-Integral closed loop control circuit FPGA PID algorithm separate interrupt function subroutine algorithm function
FPGA-based--DC-speed-controller
- 针对某船舶模型定位系统中调速电机，以FPGA(现场可编程门阵列)为控制器，采用数字比例积分调节器实现电机的速度控制算法，设计出数字化调速控制器-Positioning system for a ship model in the motor speed, the FPGA (field programmable gate array) for the controllers, proportional integral regulator with digital speed of the mo
cic_hb
- 用FPGA设计的cic和hb滤波器（积分疏状滤波器核半带滤波器）初学FPGA 的同学可以看一下啊-Using the FPGA design cic and hb filter (integral scanty shape filter nuclear half took filter)
pid
- 用现在可编程门阵列完成比例积分控制，可应用于电机转速的智能控制。-Programmable gate arrays now done with proportional-integral control, motor speed can be applied to intelligent control.
VHDL-PID
- PID Controller VHDL. It provides codes for both proportional, integral and derivative. It can be used for motor speed control, light control and others
74ls138-integral-4-wire-encoder-16
- 74ls138组成16..4线编码器 经过本人验证-74ls138 composed of 16 .. 4 line encoder after I verify
final_pp
- Piroportional Integral Code
VHDL_Divider
- 该文档详细介绍了用VHDL语言实现分数分频器和积分分频器，以及50 占空比的奇数分频和非50 占空比的奇数分频。-This document details the odd fractional divider and integral divider, and 50 duty cycle with VHDL divider and an odd number of non-50 duty cycle divide.
NCO-CIC
- 是CIC滤波器的一部分，是积分部分，可以实现3倍抽取。NCO-Is part of the CIC filter is an integral part, can achieve three times the extract.
PPM
- PPM编码 PPM的编解码方式一般是使用积分电路来实现的，而PCM编解码则是用模/数（A/D）和数/模（D/A）转技术实现的。 -PPM encoding PPM codec integral circuit, the PCM codec with analog/digital (A/D) and digital/analog (D/A) transfer technology.
cic_core
- cic积分梳状滤波器的verilog代码-the cic integral comb filter verilog code
EDA
- VHDL实现一个整点报时的秒表第一个子程序-VHDL achieve a integral point time of the stopwatch 1
VHDL-divider-design
- VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-cr
signaltext
- 信号检测，有模数转换芯片驱动，32点周期积分，判决门限2048-Signal detection, analog-to-digital conversion chip driver, 32-point cycle integral, decision threshold 2048
Prescaler-to-use-VHDL-design
- 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。-This paper describes the use of examples prescaler to use VHDL design on FPGA/CPLD, i