搜索资源列表
c19_CICfilter
- 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
digitaldownconversionbygpga
- 研究了高倍抽取的数字下变频设计，重点分析了基于级联积分梳状滤波器和级联半带滤波器的多级抽样频率算法。-Extraction of the high-powered digital down-conversion design, the focus of a cascaded integrator comb filter based on cascaded half-band filter and the multi-level sampling frequency algorithm.
AN123
- AMBA Application Note: AN123 - Logic Tile IT1 GPIO example design. -Application note AN123 provides all of the AHB slave features of AN119 with the addition of five 32bit AHB GPIO slaves. The GPIO interfaces are used to configure and test an IT1
AN136
- AMBA Application Note: AN136 - Using Core Tiles stand-alone. -AMBA Application Note: AN136- Using Core Tiles stand-alone. This example design shows how to use Core Tiles as individual units powered through an IM-LT1. A Logic Tile is also requi
cic32
- cascaded integrator comb filter 32 verilog code-cascaded integrator comb filter 32 verilog code
Integrator-comb_timing-state
- 积分梳状滤波器和时序状态机的Verilog语言描述，适合硬件描述初学者-Integrator-comb filter and timing the Verilog language to describe state machines, hardware descr iption suitable for beginners
Code
- 用于数字积分器的设计，主要涉及VHDL、Verilog等FPGA编程语言。-Design of Digital Integrator
cic3_decimator
- 积分梳状滤波器(CIC)设计，解释很清晰的，希望对大家有所启发-Integrator comb filter (CIC) design, explained very clearly, we hope to be inspired. ...
fir
- 积分梳状滤波器(CIC)设计；,有详细的步骤-Integrator comb filter ( CIC ) design
JIFENLBOQI
- 通过verilog hdl语言完成对积分梳妆滤波器的设计-By verilog hdl language used to complete the design of the integrator comb filter
Integrator
- libero环境下利用verilogHDL实现积分器功能-libero environment using an integrating function verilogHDL
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
CIC_verilog
- 采用verilog实现的三级CIC抽取器，输入8位数据，输出26位数据，使用有限状态机用于实现下采样，包括积分器实现模块和梳状器实现模块-Using verilog to achieve three CIC decimation filter, the input 8-bit data output 26-bit data, the use of finite state machines for sampling, including the integrator and comb to im
project_2
- simple gates using ip integrator from xilinx