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ad_DCT
- verilog 编程 有测试文档 基于查表结构实现 离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores
gold
- SRL16是Virtex器件中的一个移位寄存器查找表。它有4个输入用来选择输出序列的长度。使用XCV50-6器件实现，共占用5个Slice。用来生成gold码。-SRL16 Virtex devices is a shift register lookup table. It has four input used to select the output sequence length. Use XCV50-6 device, occupying a total of five Slice.
DDS_Power
- FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table thr
FPGA.rar
- 关于FPGA查找表内部结构的介绍，对查找表的建立与使用也有初步讲解 ,FPGA lookup table on the internal structure, the look-up table for the establishment and initial on the use of
NCO_based_rom
- 完整的基于ROM查找表的NCO 产生10位宽的正交信号-Integrity of the ROM-based lookup table of the NCO have 10-bit wide of the orthogonal signal
ImplementLUT-baseFIRFilterwithVHDL
- 用VHDL语言实现查找表方法有限冲击响应滤波器-VHDL language used lookup table method to achieve finite impulse response filter
RS_decoder
- Reed solomon decoder based on table-lookup method VHDL code
waveform_gen_latest.tar
- VHDL实现NCO与LUT（查找表） VHDL实现NCO与LUT（查找表）-VHDL realization of NCO and LUT (lookup table) VHDL Implementation NCO and LUT (lookup table)
xiaomei3
- 介绍了无记忆高功率放大器的非线性特性和常见的各种线性化技术，重点研究了基带查找表法预失真技术，对其进行了FPGA实现-Introduces memoryless nonlinear characteristics of high power amplifier and the common variety of linearization techniques, focus on the base-band pre-distortion lookup table method, techniqu
vhdl2
- vhdl语言正弦信号发生器设计，传统的用分立元件或通用数字电路元件设计电子线路的方法设计周期长,花费大, 可移植性差。本文以正弦波发生器为例,利用EDA 技术设计电路,侧重叙述了用VHDL 来完 成直接数字合成器(DDS) 的设计,DDS 由相位累加器和正弦ROM 查找表两个功能块组成,其 中ROM查找表由兆功能模块LPM-ROM来实现。-The traditional use of discrete components or general purpose digital cir
ROM
- Verilog sine的查找表，相信大家会用到-Verilog sine lookup table, I believe we will use
SG_FPGA
- 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the devic
vga_lcd_latest.tar
- vga lcd 控制器 24位VGA控制，支持12位DVI协议-This embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost
CRC
- 在CPLD 或者ＦＰＧＡ中实现CRC,可以查找表方式或根据原理去实现-CPLD or FPGA CRC can lookup table according to the principle
Rendering primitives
- Some 2D graphic rendering in VHDL: - Line - Draw a line - Circle - Draw circle - BitBLT - Draw a rectangle - Sine and cosinus lookup tables - Rotation - Rotate line
UART
- 一个高速串口 使用查找表写的 很省资源 来自xilinx picoblaze代码-A high-speed serial port using a lookup table to write the provincial resources
mult4x4
- 4*4乘法器的源代码，利用FPGA的查找表实现，是数字电路和FPGA的经典乘法器源代码-4* 4 multiplier source code, FPGA lookup table to achieve classic digital circuit and FPGA multiplier source code
16QAM
- 利用VERILOG语言编写的利用查找表进行16QAM调制源代码-Using a Lookup Table the 16QAM modulation source code using Verilog language
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algori
kmp_matching
- 基于fpga的字符查找KMP算法，verilog语言-Fpga-based character lookup KMP algorithm, verilog language