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vga_hex_disp.rar
- 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。,The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compilin
Chapter10
- 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
mem_ctrl_latest.tar
- 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Guagle_wave
- 这是一个波形文件产生软件 用于产生FPGA 所设计ROM的初始化波形文件memory initialization file-This is a waveform file generated by the design of the software used to generate FPGA initialization of ROM memory initialization file waveform file
NANDflash
- NAND型闪存接口程序 里面包含了datasheet以及测试程序 -NAND flash memory interface program
M25P32_VG_12_50MHZ
- Serail Nor Flash Memory Model
fifo
- 先入先出缓冲存储器，采用verilog hdl-FIFO buffer memory, using verilog hdl
cam_test
- 一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog-CAM a verified source (CAM = Content Address Memory). Language for Verilog
mig007
- XILINX memory interface generator. XILINX的外部存储器接口。-XILINX memory interface generator.
pci_t
- verilog开发的PCI target模块，能完成配置空间的读写以及单次的memory读写，原创。-Verilog development of PCI target module, to complete the reading and writing, as well as the configuration space of a single memory read and write, originality. Ha ha
Flashmemory
- Fusion的Flash memory测试，实现存储和调用。-Fusion of Flash memory testing, storage and call realize.
memory_example
- This simple example allows you to get familiar with Active-HDL s Memory Viewer.
memory
- Verilog写的内存控制器代码. 很好,很容易看懂-Verilog code to write the memory controller
memoryVHDLdesign
- memory VHDL design-memory VHDL design
memory_cores_latest[1].tar
- 存储器控制器，是Verilog描述，希望对大家有帮助！-Memory controller
del_ctrl
- A VHDL logical example of memory delay controller -A VHDL logical example of memory delay controller
cam
- This Verilog desription shows an example for a Content Adressable Memory (CAM)
RAM_Examples
- Verilog hdl code for representing ram and rom "memory" using many methods
ram
- 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个RAM存储器。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware descr iption language to achieve a RAM memory.
DSP-External-Memory-Interface-Module
- EMIF是DSP嵌入式系统中重要的外扩接口，往往连接大容量/高速存储器、并行AD/DA、外扩特殊功能芯片，甚至连接FPGA或者ASIC。-EMIF is a DSP embedded system is an important external expansion interface, often connect large-capacity/high-speed memory, parallel AD/DA, outside the extended special function chi