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gold
- SRL16是Virtex器件中的一个移位寄存器查找表。它有4个输入用来选择输出序列的长度。使用XCV50-6器件实现，共占用5个Slice。用来生成gold码。-SRL16 Virtex devices is a shift register lookup table. It has four input used to select the output sequence length. Use XCV50-6 device, occupying a total of five Slice.
dsp-book
- 数字信号处理设计参考白皮书，是期望充分发掘Xilinx DSP Slice的DSP设计人员的绝佳参考资料-Digital signal processing design reference White Paper, is expected to fully exploit the DSP Xilinx DSP Slice an excellent reference for designers
slice
- A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually inter
code3
- this slice processor-this is slice processor
DSP48E1_Slice_User_Guide
- xilinx Virtex-6 系列FPGA的DSP模块DSP48E1使用手册Virtex-6_FPGA_DSP48E1_Slice_User_Guide.-The user s guide forDSP48E1 Slice of the xilinx virtex fpga.
chipromlmp
- 片内ROM的LPM应用（适用于存储容量比较大的场合，本节具体描述的ROM为存储了256个点的SIN函数值）-Slice the application within LPM ROM
Task06_DSP48A1
- 基于Xilinx Spartan 6 FPGA的DSP48A1 slice 的使用实例-DSP48A1 slice Use examples Base of Xilinx Spartan 6 FPGA
eda
- EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时
Array_slice_1Dx1D_of-bit-vector
- Array slice 1dx1D for individual access of element
jishuqi
- FPGA应用底层开发的逻辑单元slice连线实现计数器的功能，包含代码及仿真(FPGA applies the logic unit slice connection that is developed at the bottom to realize the function of counter, including code and simulation.)