搜索资源列表
Synopsys
- Synopsys 8051 IP core documentation.
PCI_144
- -- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library --- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library
Lab11
- 32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
brentkung_adder
- Synopsys的DesignWare库中采用的brentkung高速加法器Verilog源代码生成,附相关文档
DW8051
- 大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写,能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51
vcs_simulation_mannual(Edition
- VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式.该文档是一个不错的使用指南.,VCS-verilog compiled simulator is the Synopsys company s products. Its simulation at a fairly rapid pace, and support multiple call mode. This document is a good guide.
DW8051.rar
- Synopsys 公司的DW8051源代码,用verilog编写的,代码很完整,可以仿真,对采用8051核做嵌入式的人很有帮助,Synopsys company DW8051 source code, written with Verilog, the code is complete, can be simulated using 8051 nuclear helpful people who do Embedded
The-Specification-of-SDC
- 综合约束文件SDC的写法说明 synopsys 出品-Using the Synopsys Design Constraints Format Application Note
OpenRISC
- 一个开放的risc,已应用到实际中,可以借鉴的不少,大家-an open RISC, has been applied to practice, we can draw a lot, we look at
2008.09-scripts_only
- synopsys icc 使用参考脚本-reference scr ipt of synopsys icc
ebook_verilog_fine_state_machine
- Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
VHDL
- vhdl 相关知识 指令及示例 和 Physical Level Design using Synopsys-vhdl command and example of relevant knowledge and Physical Level Design using Synopsys
ASIC_Design_Flow_Tutorial_with_synopsys
- Tutorial from VCS to IC Compiler for ASIC design using synopsys tool. .
Synopsys-RTLSystemC
- synopsys的systemc和RTl书籍清晰电子版,专业权威的EDA公司的培训资料-synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials
ASIC-SYNOPSYS
- 芯片设计综合经典书籍 design compiler primetime-asic synthesys
Synopsys-tools-intruction
- synopsys的主要的工具介绍,包括DC,PT,Formality等,对于初学IC设计者了解设计工具有很大帮助。-synopsys of the main tools for presentations, including DC, PT, Formality, etc., for the beginner tool for IC designers to understand the design of much help.
ASIC-Design-With-Synopsys
- ASIC Design With Synopsys
fifo
- 基于verilog HDL的fifo设计与测试,包含设计与测试代码,以及简单的makefile编写。整个平台是基于linux操作,仿真平台是基于SYNOPSYS的vcs工具。(Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation pla