搜索资源列表
RLC Test
- RLC Test程序,一个电子竞赛的题目。里面有详尽的源代码。-RLC Test procedures, an electronic race issue. There are detailed source code.
booth.rar
- 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码,VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
test
- Spartan-3e LED测试代码, 用SW0进行开关控制-Spartan-3e LED test code, the switch SW0
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
VHDL-test-codeBooth-multiplier
- VHDL实验代码：Booth乘法器，是一个基于VHDL语言开发的程序，非常的实用-VHDL test code: Booth multiplier, is a VHDL-based language development program, a very practical
TLC5510_IIPRAM1
- FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the
EDA-test-3
- 大学EDA实验的一些代码 都可以完美运行-University of EDA test some of the code works perfect
I2C_test
- FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.-FPGA EP2C5Q288C8 I2C original code, test that is used to open OK.
dl2c58_c5
- FPGA EP2C5Q288C8 TEST 原码,测试OK 打开即用.-FPGA EP2C5Q288C8 TEST original code, test that is used to open OK.
TestFixture
- I2C 控制器的 Verilog测试源程序-I2C controller Verilog source test
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
FPGA-SRAMt-test
- 测试型号为EP2C5Q208C8的FPGA的RAM是否正常，按提示操作，并显示每步的测试结果-EP2C5Q208C8 test models for the FPGA' s RAM and whether it is normal, according to prompts, and display each step of the test results
spi2-testbench
- test bench for spi communication
A_bit_serial_data_transmitter
- 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify th
multiplier_8_bit
- This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit)
RISC
- source and benchmark test for the registery parts of a RISC processor-source and benchmark test for the registery parts of a RISC processor
src
- i2c module. i test it on Altera FPGA.
Spartan3VGATest
- This VGA test will draw a single color page and change color every one second. VGA resolution is 640x480 @25 MHZ 8 colors
TEST-BENCH.vhd
- test bench for ddr 1
sensor-test-on-lcd
- sensor test on lcd 256