搜索资源列表
nios-II
- 很好地描述了NOISII的串口、定时中断等各种实例-A good descr iption of the NOISII the serial port, timer interrupt, and other examples of
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
gh_timer_8254
- VHDL Source code for 8254 timer/counter
gh_vhdl_lib
- VHDL Library for 8254 timer/counter core
a8254
- 自己编写的8254计数器／计时器，实现了所有的６种模式，和大家一起分享。-I have written 8254 counter/timer, realize all the six kinds of patterns, and the U.S. share.
timer
- vhdl代码：电子时钟VHDL程序与仿真！初学fpga者可以参考参考！！比较简单-VHDL code: electronic clock and simulation of VHDL procedures! FPGA beginner who can refer to reference! ! Relatively simple
ApbTimer
- PowerFull Apb Timer Controller
8253
- With realize based on the FPGA programmable timer counter 8253 designs -With realize based on the FPGA programmable timer counter 8253 designs
FPGA_jiaocheng_yu_shiyan
- 最重要的是七个从简单到复杂的实验，包括：基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ，这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写，有实验板和没有实验板的都可以用来学习。 其次还包括： FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档，很好用的文档，您下了相信不会后悔！-
timer
- VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs
timer
- 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
Timer
- ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
timer
- 基于硬件描述性语言vhdl的定时器timer的设计-timer
nios
- altera ep2c8V2 开发实例 timer uart I2C key interrupt 等-altera ep2c8V2 examples timer uart I2C key interrupt etc.
timer
- 计时器的Verilog描述 CPU设计者可以借鉴 -Verilog decription of the timer in processors
Lab2b
- A C example for Nios II to use the timer and to obtain the time execution performance
watch_dog_rtl_source
- Watchdog timer verilog RTL code
timer_rtl_source
- Timer verilog RTL code
clock
- 具有定时可调多功能数字电子钟，本人已经在fpga上调试成功-With adjustable multi-function digital electronic clock timer, I have been successful in the fpga debugging
timer
- 外设timer设计：16bit定时器、ETU计数器、具有3种可配置中断请求输出、内部寄存器的读写编程。-Peripheral timer design: 16bit timer, ETU counter, with 3 configurable interrupt request output, the internal register read and write programming.