搜索资源列表
H264
- h.264(verilog HDL) 这是基于流水线结构的H.264解码器源码-h.264 (verilog HDL) which is based on the pipeline structure of the H.264 decoder source code
13-1l
- 一个VHDL的程序,关于彩条显示的。利用FPGA的VGA显示设计的程序!-VHDL
hdl
- 图像数据的采集和处理,并通过串口发送到PC界面进行整理。-Image data acquisition and processing, and sent to the PC through the serial interface to collate.
VIDEO-FPGA
- 视频采集输出实例,FPGA视频采集和输出-Video Capture output examples
ImageProcessing
- 应用不同的用户可选择回旋滤波器的图像处理部件。一套PC应用程序将图像档案下载到一个FPGA可访问的存储器阵列。处理过的图像显示在连接的VGA显示屏上。 -Users can choose to apply a different room of the image processing filter components. A set of PC applications will be image files downloaded to a FPGA can access the memory
JPEG
- Here is a quite detailed low level design document for the Core: Low Level Design Document for JPEG Encoder
83390065FECDlg
- it is code in vhdl-it is code in vhdl
97288430FFTIFFT
- it is very large code in vhdl
49636955veriloginterleave2
- it is nice code in vhdl-it is nice code in vhdl
RGB2YUV
- RGB -> YUV转换verilog代码-RGB-> YUV verilog
DE2_LCM_CCD
- DE2上的基于FPGA的视频开发资料第1部分-DE2 video(part one)
GUI_Matting
- matlab编写的交互式image matting程序,包括:Poisson,Hillman,Ruzon等方法和源图像-matlab interactive image matting procedures, including: Poisson, Hillman, Ruzon methods and sources image
CCD
- 对ccd图像进行解码采集,并通过VGA输出-Ccd image decoding of the collection, and through the VGA output
shiftregister_32
- 长度为8的32bit串入并出移位寄存器,它的功能就是对32bit的并行信号作串行输入,并行输出处理-Length of 8 for 32bit serial in parallel out shift register
rls
- 是二阶RLS自适应均衡的实现,采用V—LOG编写而成,是从工程中截取的 可以直接应用-Second-order RLS adaptive equalizer is the realization of the use of V-LOG prepared is intercepted from the project can be applied directly
zzz
- FPGA大赛的优秀论文。T3A智能型公交车站牌、基于Nios的指纹识别系统、家庭便携式远程医疗监护仪 。-FPGA Contest outstanding papers. T3A smart card bus station, the Nios-based fingerprint identification system, the family of portable telemedicine monitor.
1
- 一维离散小波变换的VLSI设计很好的学习资料-One-dimensional Discrete Wavelet Transform VLSI design of good learning materials
VGA
- 一个VGA显示的简单例子,学习如何做VGA显示-VGA shows a simple example, learning how to do VGA display
reg1
- Register1 Project VHDL