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VHDL
- odule vga_timing ( input wire clk_i, //输入时钟 40MHz input wire reset_i, //输入复位信号 output wire vga_pixel_flag, //输出像素有效 output reg vga_line_o, //输出水平信号 output reg vga_field_o, //输出垂直信号 output reg vga_frame_o //输出帧开始信号 ) //////////
1245_COR
- simulink of mobile robot vhdl and ise matlab progra-simulink of mobile robot vhdl and ise matlab programm
expand
- 用VHDL语言实现屏幕保护程序，用IPcore储存衣服图像-Just as
hdmiadvi-Demo
- HDMI & DVI interface reference verilog and VHDL code
PBDC
- Verilog is a one of the famous Hardware Descr iptive Languages (HDL). (VHDL is the other one). Verilog langauage syntax very well matches with C language syntax. This is big advantage in learning Verilog. Logic operators, data types, loops are simila
image-denoising
- 基于FPGA的图像降噪处理，用vhdl实现，对校验噪声有良好的效果。顶层文件是sram_1024_top.vhd，综合连线文件在DIME文件夹中，与FPGA通信的文件在C文件夹-FPGA based image denoising by vhdl, works well when dealing with salt and pepper noise,top level is sram_1024_top.vhd
2f0d6763eae7
- yuv2rgb vhdl语言 可以将yuv格式图像转换为rgb格式，非常好用- The code can be converted to a YUV image data of RGB VGA monitor can display the data, R, G, B of the bit width of 4, the conversion speed.
med_filter
- 基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波-Based on the median filter VHDL source image processing, image filtering can be achieved
dct_latest.tar
- dct最新的 vhdl代码，给予lgpl，需要的可以-dct latest vhdl code, giving lgpl, need to look
GaussSmooth
- 图像处理，高斯平滑（VHDL）实现了去除高斯噪声的功能，希望对大家有帮助-Image processing, Gaussian smoothing (VHDL)
pal
- FPGA产生PAL-D的VHDL和Verilog代码。-The code is used to generate the sequence of PAL with FPGA in VHDL and Verilog
structural-sequence-recog
- vhdl code for sequence recognizer
hough_5289
- hough变换的vhdl程序设计，测试没有任何问题，可以执行，开发工具quartus，modelsim-hough transform with fpga and vhdl ，good tested and you can use it happily
fpga_generic_egs
- VHDL FPGA 图像处理 数字信号 LSB嵌入-VHDL FPGA image processing digital signal LSB embedding
pld_bisai
- 东南大学pld竞赛获奖代码，比较有价值，vhdl语言编写-Southeast University pld race winning codes, more valuable, vhdl language
8sfdsd
- 用VHDL实现的八位可逆计数器，可作为交流学习使用。-VHDL implementation with eight reversible counter can be used as the exchange of learning to use.
vhdl
- 中值滤波 中值滤波 中值滤波 中值滤波 中值滤波 -Midian filter
lab12_design_files
- des code source vhdl sur fpga-des code source vhdl sur fpga
VHDLFIR
- 1 由matlab计算FIR数字滤波器的滤波系数； 2 用VHDL语言设计逻辑电路，再通过QUARTUS II 软件，将各个模块的电路封装成期间，在顶层设计中通过连线，完成整个系统。 -matlab VHDL QUARTUS
vga256
- 用VGA显示256种颜色，初步学习VGA的原理和VHDL语言的方法-learn VHDL and use VGA to 256 color