pld/
pld/.Xil/
pld/.lso
pld/DATA.cmd_log
pld/DATA.prj
pld/DATA.spl
pld/DATA.stx
pld/DATA.sym
pld/DATA.v
pld/DATA.xst
pld/_ngo/
pld/_ngo/netlist.lst
pld/_xmsgs/
pld/_xmsgs/bitgen.xmsgs
pld/_xmsgs/map.xmsgs
pld/_xmsgs/ngdbuild.xmsgs
pld/_xmsgs/par.xmsgs
pld/_xmsgs/pn_parser.xmsgs
pld/_xmsgs/trce.xmsgs
pld/_xmsgs/xst.xmsgs
pld/cai_ji.cmd_log
pld/cai_ji.prj
pld/cai_ji.spl
pld/cai_ji.stx
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pld/caiji.v
pld/choose.cmd_log
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pld/conture.cmd_log
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pld/datacatch.cmd_log
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pld/datachoose.cmd_log
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pld/datatest.cmd_log
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pld/decode.cmd_log
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pld/detect.cmd_log
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pld/din_shi.cmd_log
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pld/div.cmd_log
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pld/equal.cmd_log
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pld/ipcore_dir/
pld/ipcore_dir/_xmsgs/
pld/ipcore_dir/_xmsgs/cg.xmsgs
pld/ipcore_dir/_xmsgs/pn_parser.xmsgs
pld/ipcore_dir/coregen.cgp
pld/ipcore_dir/coregen.log
pld/ipcore_dir/create_fifo.tcl
pld/ipcore_dir/create_ram.tcl
pld/ipcore_dir/create_ram1.tcl
pld/ipcore_dir/create_ram2.tcl
pld/ipcore_dir/create_rom.tcl
pld/ipcore_dir/ram/
pld/ipcore_dir/ram/blk_mem_gen_v7_1_readme.txt
pld/ipcore_dir/ram/doc/
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pld/ipcore_dir/ram/doc/blk_mem_gen_v7_1_vinfo.html
pld/ipcore_dir/ram/example_design/
pld/ipcore_dir/ram/example_design/ram_exdes.ucf
pld/ipcore_dir/ram/example_design/ram_exdes.vhd
pld/ipcore_dir/ram/example_design/ram_exdes.xdc
pld/ipcore_dir/ram/example_design/ram_prod.vhd
pld/ipcore_dir/ram/implement/
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pld/ipcore_dir/ram/implement/implement.sh
pld/ipcore_dir/ram/implement/planAhead_ise.bat
pld/ipcore_dir/ram/implement/planAhead_ise.sh
pld/ipcore_dir/ram/implement/planAhead_ise.tcl
pld/ipcore_dir/ram/implement/planAhead_rdn.bat
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pld/ipcore_dir/ram/implement/xst.prj
pld/ipcore_dir/ram/implement/xst.scr
pld/ipcore_dir/ram/simulation/
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pld/ipcore_dir/ram/simulation/bmg_stim_gen.vhd
pld/ipcore_dir/ram/simulation/bmg_tb_pkg.vhd
pld/ipcore_dir/ram/simulation/checker.vhd
pld/ipcore_dir/ram/simulation/data_gen.vhd
pld/ipcore_dir/ram/simulation/functional/
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pld/ipcore_dir/ram/simulation/functional/simulate_isim.bat
pld/ipcore_dir/ram/simulation/functional/simulate_mti.bat
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pld/ipcore_dir/ram/simulation/functional/simulate_ncsim.sh
pld/ipcore_dir/ram/simulation/functional/simulate_vcs.sh
pld/ipcore_dir/ram/simulation/functional/ucli_commands.key
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pld/ipcore_dir/ram/simulation/functional/wave_mti.do
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pld/ipcore_dir/ram/simulation/ram_synth.vhd
pld/ipcore_dir/ram/simulation/ram_tb.vhd
pld/ipcore_dir/ram/simulation/random.vhd
pld/ipcore_dir/ram/simulation/timing/
pld/ipcore_dir/ram/simulation/timing/simcmds.tcl
pld/ipcore_dir/ram/simulation/timing/simulate_isim.bat
pld/ipcore_dir/ram/simulation/timing/simulate_mti.bat
pld/ipcore_dir/ram/simulation/timing/simulate_mti.do
pld/ipcore_dir/ram/simulation/timing/simulate_mti.sh
pld/ipcore_dir/ram/simulation/timing/simulate_ncsim.sh
pld/ipcore_dir/ram/simulation/timing/simulate_vcs.sh
pld/ipcore_dir/ram/simulation/timing/ucli_commands.key
pld/ipcore_dir/ram/simulation/timing/vcs_session.tcl
pld/ipcore_dir/ram/simulation/timing/wave_mti.do
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pld/ipcore_dir/ram.asy
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pld/ipcore_dir/ram.ncf
pld/ipcore_dir/ram.ncf.baiduyun.uploading.cfg
pld/ipcore_dir/ram.ngc
pld/ipcore_dir/ram.sym
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pld/ipcore_dir/ram.xco
pld/ipcore_dir/ram.xise
pld/ipcore_dir/ram2/
pld/ipcore_dir/ram2/blk_mem_gen_v7_1_readme.txt
pld/ipcore_dir/ram2/doc/
pld/ipcore_dir/ram2/doc/blk_mem_gen_ds512.pdf
pld/ipcore_dir/ram2/doc/blk_mem_gen_v7_1_vinfo.html
pld/ipcore_dir/ram2/example_design/
pld/ipc