搜索资源列表
i2c.tar
- i2c总线控制器ipcore，包含testbench
sram
- sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation
XiaYuWen_8_RISC_CPU
- 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶
FinalCodelast
- last cordic for immplemantaion of cordic with vhdl language it has testbench
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
counter
- 8bit counter testbench modeling source file
ethernet_tri_mode_latest[1].tar
- ethernet_tri_mode from opencores.org inlcude rtl and testbench
tebench_seq
- this sequence circuit testbench, in logic , aginst combinational . Verilog HDL .v-this is sequence circuit testbench, in logic , aginst combinational . Verilog HDL .v
uart
- verilog实现UART收发源码 内有testbench-the UART transceiver Source for verilog implementation With testbench
7-to-3
- 写出七到三化简表达式并用verilog实现，与传统全加做比较。（内含testbench）-Write seven to three simplification expression verilog achieve, compared with the traditional full. (Including testbench)
Chapter-7
- 7.2 I2C Master Controller设计 7.3 I2C Master Controller Testbench设计-7.2 I2C Master Controller Design 7.3 I2C Master Controller Testbench Design
Chapter-8
- 8.2 CAN Protocol Controller模块设计 8.3 CAN Protocol Controller Testbench设计 -8.2 CAN Protocol Controller Module Design 8.3 CAN Protocol Controller Testbench Design
Chapter-12
- 12.2 ATA主机控制器设计 12.3 ATA主机控制器Testbench设计 -12.2 ATA host controller design 12.3 ATA host controller Testbench Design
Chapter-13
- 13.2 RISC-CPU设计 13.3 RISC-CPU Testbench设计-13.2 RISC-CPU design 13.3 RISC-CPU Testbench Design
ethenete
- 基于verilog的三速以太网源程序，文件中包含源程序和测试程序。-tri_model ethernet source code based on vhdl languange, include source code and testbench in the file.
ALU
- 简易的VHDL程序，主要实现ALU的逻辑功能，进行选择和数据的移动。很适合初学者对VHDL的理解。内含有testbench可以进行Qutarus的仿真-Simple VHDL program, the main achievement of the ALU logic functions, to select and move data. VHDL is suitable for beginners to understand. Containing a simulation testbench
lab-assignment1
- 这个是计算机结构的实验内容,主要包括逻辑门的设计(例如:与门,或门,非门).此外还有testbench的设计代码.-This is a computer architecture in experiments, including the design of logic gates (for example: AND gates, OR gates, NAND gate). Addition testbench design code.
CMOS_proj2_RTL
- 用上位机UART控制一个十字路口的交通灯的.v文件。包括testbench在内，可用FPGA cycloneII DE270跑仿真。-traffic lights at a crossroads. V file controlled by PC UART. Including testbench , available FPGA cycloneII DE270 run the simulation.
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
Testbench--Study
- testbench顾名思义就是一个测试台，它对外没有接口，所以实体部分为空，但它要对要测试的器件提供激励信号，这其实就是最简单的testbench，本文介绍了Testbench的书写-testbench name suggests is a test bed, it is no interface to the external, physical part of it is empty, but it should provide a stimulus to the device under