搜索资源列表
m16550a_verilog_rtl
- mentor UART IP verilog源码 以通过验证.-mentor UART IP verilog source to the test.
FSM_Westor
- 状态机得用法,可以帮助新手了解状态机得用法以及掌握用途-state machine in use, and can help newcomers understand the state machine in use, and control purposes
keyscan
- 4×4键盘扫描的verilog 代码,在CPLD板上实现
SmartSOPC_Board_Cyclone_1C6
- sopc开发板标准NIOSII模块,用于EP1C6Q240C8芯片(FPGA)
aFifo
- verylog语言编程,为异步flipflop的程序。具有数据传输功能,数据位数可以用户设定
mycpu
- Quartus II 5.0下写的一个单总线架构的CPU设计,包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。
nlint+debussy+modelsim
- modelsim + debussy脚本
an500_design_example
- 利用MAX II CPLD 实现 NAND 闪存接口
mouse1
- PS2鼠标驱动程序,verilog语言书写
DE0 Debounce
- DE0 SPEC
pllverilog 完成pll锁相环的设计
- 基于FPGA的程序编写,完成pll锁相环的设计,实验证明次程序是完整的-FPGA-based programming, complete pll PLL design, experiments show that second program is complete
apb.rar
- APB master verilog code,APB master verilog code
booth_multiplier
- Booth multiplier written in verilog
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现,功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
generic_fifos
- Generic FIFO for use with both xilinx and altera
apb_uart
- 基于APB总线的UART详细设计方案和实现-APB-based detailed design and implementation of UART
SmartSOPC_Flash_Programmer
- nios 嵌入式系统基础教程实验 创建目标板FLASH编程-Nios Embedded System Essentials experiment to create target board FLASH Programming
SmartSOPC_standard_1c6
- nios 嵌入式系统基础教程配套实验 定制基于AVALON总线的用户外设实验-Nios Embedded System Essentials custom matching experimental bus-based user peripherals AVALON experiment
02_CPLDxitong
- cpld系统 EWB Quartus2编译 电子综合设计试验箱程序-CPLD system compiler EWB Quartus2 chamber electronic integrated design process
clk4
- clk4 时钟分频设计用于FPGA入门设计-clk4 clock divider is designed for FPGA design entry