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erjinzhiyunsuan
- 基于simulink的二进制运算，通过simulink建模，然后生成代码在quartus下仿真。-Simulink based on the binary operator, through the simulink model, then generate code in Quartus Simulation.
tcc_cdma
- full testbench design including random number generator, the tcc encoder, the tcc decoder and some control logic.
JPEGEncoderVerilog
- encoder jpeg project
alu8bit
- alu8bit.Usefull in design simple CPU(for beginner)
rom
- design a module (ROM)in design simple CPU
GPIO
- GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-state bus interface-Use verilog to design a 48 control points that can be programmed to input or output controller
led_test1
- 在de2板上的led流水灯显示 C语言实现 实验环境Quartus2+nios2-De2 board in the water led light shows C language environment for the realization of the experiment Quartus2+ nios2
display
- 这是一个给予FPGA的动态显示代码，是利用verilogHDL实现的-It is a dynamic display of the FPGA code, the use of verilogHDL to achieve the
Lab1
- My first project written in Quartus II by using VHDL, executed some tasks that display word on 7-segments LED through the simulated 5-to-1 multiplexer. My code is easy to acquire and may be help usefull.
chengfa
- 用VerilogHDL的16*16乘法器的设计实现，采用的是移位相乘方法-VerilogHDL with 16* 16 multiplier design using the method of displacement multiplied
61EDA_D1049
- 频率计设计６位数码管还是拉倒机是大撒但是的撒但是 -6 Cymometer design digital control machine or leave it is spreading
jc2_ver
- Johnson counter with verilog
watchver
- watchdog with verilog
serial1
- 串口简化verilog模型，固定波特率4.8k, 输入、输出使能输出-Verilog model of serial simplified
pong
- software testing code and debugging using vhdl
labs
- Xilinx embeded system labs
year
- 工程备份综合教程,主讲的数学用法,建议大家下载-Integrated Course backup works, the use of mathematical topics, it is recommended you download
newcode
- ram block discr iption ,which are fullfill all kind of fuction that you need-ram block discr iption, which are fullfill all kind of fuction that you need
fpadd
- It is the floating point data type adder!
Altera_Proj
- altera nios ii ide c code