搜索资源列表
xapp265
- High-Speed Data Serialization and Deserialization(840 Mb/s LVDS) for xilinx fpga
seg7led
- 点亮7位LED小灯实验 基于hdl语言 有全部管脚锁定等-seven leds based on verilog hdl
clz
- 对于一串二进制数前置零的计数的Verilog程序-For a string of binary zero count Verilog pre-procedure
bai2
- excercises verilog add two bcd numbers
part6
- run hello on 7-segments led on de2 board using verilog
part4
- d flipflop using verilog
bai4
- a 16 bits counter using verilog
a_time_counter_using_verilog
- a time counter using verilog
a_bcd_counter_using_verilog
- 3 bits bcd counter using verilog
source_code
- verilog code fifo memory usb
PC_IR
- PC & IR & &decoder and with its test bench
FIFO
- FIFO(first in first out) design written in Verilog
stopwatch
- check the design people
DAC
- 主要实现对DA转换器的控制、调试程序，使用Verilog语言实现其功能-Main achieved control of the DA converter, debugger, use the Verilog language function
Watch
- Design Watch with set time by Verilog for kit DE2
Counter_from_0_to_100
- Counter: Count from 0 to 100, increase count after 1s
eetop.cn_ces_vmm_2006.06-SP1.tar
- vmm introduction material. it is a good file.
ram_top
- arm ahb slave bus sram ip in verilog
robotic_arm
- An effort has been made to design a robot, which loads and unloads an object to the station depending on the request. The sensor connected to the robot will sense the request and initiate the correct sequence of operation. The robot under design has
project
- project in data structure good for making radix sort