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list_ch06_05_div
- Because of complexity, the division operator cannot be synthesized automatically. We use an FSMD to implement the long-division algorithm in this subsection.
rtc
- RTC读取 系统时钟设计 数码管点亮 I2C 实现-RTC读取 系统时钟设计 数码管点亮 I2C 实现
digital-clock
- 秒表,可以计时，还有秒表功能，还能设置时间-digital clock
ok
- 用fpga的lcd显示汉字云南大学……，寄存器写数字符码-To fpga' s lcd display Chinese characters Yunnan University ... register to write a few character code
noor
- it shows Johnson counter
action_vip_music
- VHDL写的音乐程序，配套硬件，音乐播放器实验-VHDL write music program, and form a complete set of hardware, the music player
digital-Timer
- 数字时钟，使用Verilog实现，已经调试过了-Digital clock, using Verilog implementation
uart_if
- FPGA与串口通信的控制程序，通过程序控制通信的配置接收和发送。-FPGA with serial communication control procedures, through program control communication configuration receiving and sending.
fifo_232
- 基于fpga串口fifo设计，经本人测试，可用-Fpga serial fifo design after my test, available
ALU
- 计算机ALU的verilog设计，能够实现加减与或运算-Computer ALU verilog design can add and subtract with or computing
rc5
- abiut rc4 implementation
3x3
- 这是可编程器件的其中之一，可以编程解决问题-This is one of the programmable devices can be programmed to solve the problem
ledflow
- led流水灯工程，方便大家好好的学习FPGA-led light water engineering, facilitate proper learning FPGA
sram_test
- SRAM 测试的verilog 及NIOS II 全部代码。-SRAM testing verilog NIOS II code.
pal.rar
- PAL制式时序发生verilog模块，13.5MHz，频率可以改,PAL video timing generator verilog modules, 13.5MHz, the frequency can be changed
Elevator5
- elevator controller implemented on DE2 board
ripplecarryadder
- ripple carry adder in verilog
FPGA_lcd12864
- 基于FPGA的12864驱动代码，为verilog语言。-FPGA-based 12864 driver code, verilog language.
down_fft_2_core_right
- this file contains a project,which serves to perform fft quicker.
DLX_verilog
- 自动停车场,实现对车位的控制或管理，以达到动态控制车位的目的。-the auto park