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18.uart
- 用Verilog HDL编写的uart程序，亲测可行，注释很详细！-Written using Verilog HDL uart program, pro-test is feasible, very detailed notes!
shuzipaobiao
- 数字跑表，具有复位，暂停，秒表计时等功能。分为时钟输入，复位和启动，暂停。。。 复位信号高电平有效，可对跑表异步清零。-Digital stopwatch with reset, suspend, stopwatch and other functions. Divided clock input, reset, and start, pause. . . Active high reset signal, can stopwatch asynchronous clear.
vga_timing
- 基于Verilog的VGA控制器，经测试可以正常运行。-Verilog-based VGA controller, the test can be run properly.
spigpio_latest.tar
- SPI TO GPIO CODE HDL-SPI TO GPIO CODE HDL
DPSK_modulate
- verilog实现DPSK的调制是基于DDS直接频率生成-verilog realize DPSK modulation
scan-led
- 7段共阳极数码管，译码显示，Verilog HDL程序-Code based on Verilog HDL
key_debounce
- 按键去抖动，Verilog HDL语言，比较按键去抖和不去抖的区别
vga_sync
- vga synchronization in verilog
dcache_system-(1)
- 利用 d_cache來計算hit 及 read/write，利用cache-using cache to calculate the number of read/write and hit
random
- 利用LFSR來產生出random的數字讓FPGA能一直出現亂數-using LFSR to complete the random number