搜索资源列表
bai4
- a 16 bits counter using verilog
a_time_counter_using_verilog
- a time counter using verilog
a_bcd_counter_using_verilog
- 3 bits bcd counter using verilog
source_code
- verilog code fifo memory usb
PC_IR
- PC & IR & &decoder and with its test bench
FIFO
- FIFO(first in first out) design written in Verilog
stopwatch
- check the design people
pwm
- 用FPGA实现PWM控制输出，可以控制灯的亮暗-PWM
DAC
- 主要实现对DA转换器的控制、调试程序，使用Verilog语言实现其功能-Main achieved control of the DA converter, debugger, use the Verilog language function
firfilter14
- 用Quartus II实现综合布线，要求充分利用Altera Stratix/Stratix II的器件的DSPBLOCK资源，Quartus II综合出的系统最高工作频率达到270Mhz以上.用Verilog进行编程。-Pipeline FIR structure。
chuanbing
- 串并转换器的verilog源代码带testbench文件-String and converter verilog testbench file with the source code
Watch
- Design Watch with set time by Verilog for kit DE2
Counter_from_0_to_100
- Counter: Count from 0 to 100, increase count after 1s
eetop.cn_ces_vmm_2006.06-SP1.tar
- vmm introduction material. it is a good file.
ram_top
- arm ahb slave bus sram ip in verilog
Transmitter
- 这里上传的资料是：基于FPGA的OFDM系统开发的发送程序，涵盖了OFDM系统所有的技术点，是基于vreilog开发的。-From here the information is: FPGA-based OFDM system development send program covers all the technical point of OFDM system is based on vreilog development.
robotic_arm
- An effort has been made to design a robot, which loads and unloads an object to the station depending on the request. The sensor connected to the robot will sense the request and initiate the correct sequence of operation. The robot under design has
CPU
- GOOD PERFORMANCE CPU
project
- project in data structure good for making radix sort
Ssg_decoder_BL
- 7 segment , it present how to put the bloc SSG_decoder