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MyClockTest
- 这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time,
Counter60min
- VHDL语言编写的一个六十进制计数器（用于分钟），一个脉冲输入引脚，一个复位引脚，8个BCD码输出引脚，一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。-A 60 binary counter(for minute) programmed with VHDL language.A pulse input, a reset input, eight BCD code output BCD code, a carry bit output. It is one of my total 9 m
shizihong
- 用VHDL语言编写数字钟的程序，实现数字钟的几个功能，如计时、校时、闹钟和整点报时-Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime
EDACLOCK
- 用VHDL语言编写数字钟的程序，实现数字钟的完整功能，如计时、校时、闹钟和整点报时-Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
VHDLclock
- 这是用VHDL语言编写的数字钟。可以设置时分秒，还可以整点报时。-This is the VHDL language with the digital clock. When every minute can be set, but also the entire point of time.
shuzizhong
- 可预置数字钟，用VHDL语言编写，LED显示，普通数字钟表。-Digital clock can be preset using VHDL language, LED display, an ordinary digital watch.
shuzizhong
- 这时用VHDL语言编写的多功能数字钟，具有正常的计时功能，还能进行校时、校分，并且具有整点报时功能-Then with the VHDL language multi-functional digital clock, with the normal timing functions, but also to the school, the school hours, and have the whole point timekeeping function of
clock
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
digital_clock
- 用于FPGA可编程逻辑器件的VHDL语言编写的6显示数字钟程序。51单片机驱动6个LED数码管。-Digital clock (VHDL language) for FPGA Development
shuzizhong
- VHDL语言编写的数字钟的模拟程序，可以实现定时，时分秒的显示等-Digital clock written in VHDL simulation process can be achieved regularly, minutes and seconds of display time
exp5_clock
- VHDL语言编写的数字钟 具有清零、暂停、调整时间等功能-VHDL language of the digital clock has a clear, pause, adjust the time function
VHDLdigitalclocktimer.
- 用VHDL语言编写的数字钟程序，可以实现计时功能，且具有整点报时功能，能够实现时、分、秒的十进制显示。-With VHDL language，it can realize the function of digital clock timer.
clock
- 多功能数字钟，VHDL语言编写；是EDA学习中常见问题-CLOCK
DigitalClock
- 该数字钟，采用VHDL语言编写，具有即时，跑表，调时，调分，闹铃等功能，另外还可以增加一些功能，例如正点报时等-The digital clock, using VHDL language, with real-time, PaoBiao, adjustable, adjustable, alarm functions, also can add some functions, such as punctual
Written_in_VHDL_Digital_Clock_Design
- VHDL语言编写的数字钟设计Digital Clock Design,电子系很经典的实验设计-Written in VHDL, Digital Clock Design Digital Clock Design, Department of Electronic Engineering is the classic experimental design
Counter60sec
- VHDL语言编写的一个六十进制计数器(用于秒)，一个脉冲输入引脚，一个复位引脚，8个BCD码输出引脚，一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。 -A 60 binary counter（for second） programmed with VHDL language.A pulse input, a reset input, eight BCD code output. It is one of my total 9 modules that are used to de
digitai-clock
- 通过使用VHDL语言编写程序实现了数字钟的功能-Through the use of VHDL language procedures for the realization of the digital clock function
数字钟
- fpga课程中用vhdl语言编写的数字钟 输出到板子上是，就是一个数字时钟
shuzizhong
- 数字电子钟设计，包括时、分、秒模块，文件中包括使用VHDL语言编写源码以及原理图（时、分、秒模块）(Digital clock source as well as schematic)