搜索资源列表
booth.rar
- 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码,VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
modulation.rar
- verilogHDL编写的QPSK选相法调制模块,在ISE软件中仿真过,可综合,绝对是正确的,verilogHDL preparation phase of the QPSK modulation selection module, in the ISE simulation software that can be integrated, is absolutely correct
lab.rar
- verilog hdl经典例程,全部调试通过,verilogHdl example,all can be used
verilogHDL.rar
- 采用有限状态机(要求“三段式”)的方法设计一个带异步清零端的同步可逆模6计数器。同时提供单数码管数字显示和3LED状态显示两种显示方式。,Finite state machine (request, quot Threequot) approach to design a client with Asynchronous Clear reversible synchronous counter module 6. At the same time providing a single digit
SRAM
- VerilogHDL语言读写SRAM内部数据。SRAM芯片型号为61WV102416ALL,即1024K字,每字16位,共16Mb。工作在100MHz频率下。-VerilogHDL language to read and write internal data SRAM. SRAM chip model 61WV102416ALL, ie 1024K words, each word 16, a total of 16Mb. Work in the 100MHz frequency.
Chapter10
- 第十章的代码。 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相
verilogsram
- FPGA开发板上的VerilogHDL编写的SRAM读写试验程序, 包括介绍文档, Verilog源码, 在Quartus II 8.1环境下测试通过-FPGA development board SRAM VerilogHDL prepared to read and write test procedures, including the descr iption document, Verilog source code, the Quartus II 8.1 environment te
8b10bverilog
- 基于verilogHDL语言的8b10通信变换。-verilog 8b10b
ads7887
- 使用VerilogHDL语言实现ADS7887的时序功能。-Use VerilogHDL language ADS7887 timing function.
DS1302
- 基于VerilogHDL编写的时钟管理芯片DS1302实验开发程序。-VerilogHDL prepared based on clock management chips DS1302 experimental development program.
USB2_0
- USB2_0控制器CY7C68013与FPGA接口的VerilogHDL实现.rar-CY7C68013 and FPGA controller USB2_0 interface VerilogHDL achieve. Rar
AD9954_test
- AD公司DDS芯片AD9954的Verilog测试程序-VerilogHDL test program of DDS chip--AD9954 ,producted by AD company
CIC
- 积分梳妆滤波,介绍了积分梳状滤波器(CIC)设计,压缩包里面有程序的流程图,采用verilogHDL编写-jifenshuzhuanglubo
FFT
- OFDM系统中FFT的VerilogHDL语言实现-FFT of OFDM system VerilogHDL language
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例,详细地讲解了Verilog HDL程序设计语言,全书共分13章,内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等,实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
ep_rom
- 采用VerilogHdl语言编写的,介于FPGA的EPROM的开发读写-VerilogHdl the use of languages, ranging from the development of FPGA to read and write the EPROM
debounce_2_Verilog
- 用VerilogHDL编写的按键消抖程序 分频产生100Hz的按键采样时钟,采样时钟周期为10ms, 按键按下后,产生时间为10ms的低电平信号,即LED亮10m-*Project Name :debounce *Module Name :debounce *Target Device :Any Altera FPGA/CPLD Device *Clkin : 50MHz *Desisgner : zhaibin *Date : 2011-11-
fir
- verilogHDL编写的低通滤波器模块,在ISE软件中仿真过-verilogHDL prepared by low-pass filter module, in the ISE simulation software have been
lift-verilogHDL
- 利用verilog语言实现一个简单的电梯控制,可借助最小系统开发板进行试验-control lift by using verilong HDL
VerilogHDL
- 用Verilog HDL语言编写的跑马灯小程序,可直接在FPGA上运行-With the Verilog HDL language of the Marquee applet can be run directly on the FPGA