搜索资源列表
Altera-Recommended-HDL-Coding-Style
- Altera 推荐的HDL编码风格，在学习HDL的时候比较重要，另外对HDL到RTL的映射有一定的帮助。-Altera Recommended HDL Coding Style
Altera-FPGACPLD
- Altera FPGACPLD设计(基础篇)配套光盘,提供了书中所有示例的完整工程文件、设计源文件和说明文件。 每个工程示例都包括了该工程的项目文件、源文件、报告文件和生成结果等文件，读者可以用Quartus II或相应的软件直接打开。设计源文件根据设计输入类型分为源代码或原理图等。-Altera FPGACPLD Design (fundamental) supporting CD-ROM, the book provides a complete project files for al
Protel99_lib_ALTERA
- 比较全的ALTERA芯片的原理图和封装库(Protel99)，对需要画Altera FPGA PCB版图的同志很有用。-Comparing all the ALTERA chip schematic and footprint library (Protel99), on the need to draw Altera FPGA PCB layout comrades useful.
sls_sram_16_bit
- altera NIOS软核系统中构建外接SRAM接口的例子-altera NIOS soft-core system to build external SRAM interface example
Altera_Verilog_Coding_Style
- Altera公司的Verilog编程风格 Altera_Verilog_Coding_Style-Altera' s Verilog programming style Altera_Verilog_Coding_Style
example
- altera cpld EMP1270开发板例子程序，包括任意波形发生器，串口等-altera cpld EMP1270 development board examples of procedures, including arbitrary waveform generator, serial port, etc.
c4gx_f896_host_ddr2a_odt
- ALTERA PCIE FPGA开发板（EP4C平台）DDR2内存测试代码-ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code
1
- PCIE 与DDR的接口范例，由altera提供-PCIE and the DDR interface examples provided by the altera
DE0_Datasheet
- Altera DE0开发板的资料，他的datasheet-Altera DE0 development board information, he datasheet
Altera-NIOS32-V220
- 一个测试端口测试程序-A test port test procedures
Altera_lib
- 压缩包提供altera公司逻辑器件的标准封装，共有8百多个器件，可以供用户选择，封装格式均用protel99SE。-Altera compressed package provided by the company
I2C
- i2c ipcore of altera fpga that uses ahdl lauguage.
CycloneIII_SB_3C25
- Altera的CycloneIII Start Board,使用的PFGA是3C25，包括原理图和PCB，用Cadence Allegro打开-Altera
miniUART
- 自适应波特率的通用异步串行接口电路（ＵＡＲＴ）的ＶＨＤＬ源码，在ＡＬＴＥＲＡ上运行成功-Adaptive baud rate of the universal asynchronous serial interface circuit (UART) the VHDL source code, to run successfully in ALTERA
make_interrupt_vector
- altera NIOS软核系统 中断矢量使用例子，基于C语言-altera NIOS soft-core system interrupt vector to use examples, based on the C language
DE2_VGA3
- The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow
ref-sdr-sdram-verilog
- 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
EPM7032-7128
- altera 公司的EPM7032和EPM7128的DATASHEET-altera s EPM7032 and EPM7128 of DATASHEET
AlteraFPGACPLD1
- Altera FPGA_CPLD设计 基础篇-Altera FPGA_CPLD Part Design
Fifo
- 一个FIFO源代码，基于Altera FPGA-A FIFO source code, based on Altera FPGA