搜索资源列表
OpenSPARC_DDR2_controller_RTL_
- 基于FPGA的DDR2控制程序，用verilog编写的。,FPGA-based DDR2 control procedures, prepared by using Verilog.
Micron_SDRAM_DDR2Simulation_mo
- DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme,DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
DDR2_Memory_Test
- DDR2 controller which contains verilog files，pdf and so on
vga_control
- vga 控制器的verilog 源码 ，fpga上可实现图片的显示-vga controller Verilog source code, fpga achievable picture display
DDR2Controller
- DDR2 Controller DDR2 Controller
ddr2sdram_spartan3s700an.tar
- It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Sparta
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
- verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
ddr2
- 基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
c_xapp454
- 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and t
AMBA
- 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
DDR2_controller
- DDR2控制器IP的设计与FPGA实现，使用verilog语言-DDR2 Controller IP Design and FPGA implementation, use the verilog language
ssss
- spartan—3a对ddr2读写控制源程序，有verilog和vhdl版本-spartan-3a ddr2 read and write control of the source, there are versions of verilog and vhdl
NET2
- This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, usi
ddr
- 利用硬件verilog语言实现DDR2功能，对信息快速存储-VERILOG DDR2
DDRCHv11
- Source code for ddr2 dram controller for BEEE
DDR2-verilog
- Verilog程序设计实例中，DDR部分的程序代码-Verilog programming example, DDR part of the program code
DDR2-verilog
- ddr2的Verilog代码，包括时序控制，数据读取，利用verilog编写的ddr2控制器，在spartan6板子上得以验证，成功实现了FPGA与DDR2的通信。-ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the
ddr2_module
- 设计的DDR2的verilog代码.改代码实现读取DDR2的数据。(the code for DDR2.It is used for reading the data of DDR2)
DDR2_Control
- 参考例程之Verilog之实现DDR2时序控制实现，ISE开发平台完整工程(Implementation of DDR2 timing control implementation of reference routine Verilog, complete engineering of ISE development platform)