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origen_s5pv310_eva_cpuboard Samsung S5PV310 Exynos 4210处理器
- Samsung S5PV310 Exynos 4210处理器,CORTEX A9 双核，支持DDR3-Samsung S5PV310 Exynos 4210 processor, CORTEX A9 dual-core, support for DDR3
2048Mb_ddr3
- 美光DDR3存储器模型，用verilog语言编写，通用模型-DDR3 MEMORY
ddr3_altera_use
- altera kit gx4 上DDR3 控制器的使用-altera kit gx4 on the use of DDR3 controller
DDR3_user_design
- 在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制-On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control
sp605_MIG_rdf0029_13.1_c
- ISE MIG（DDR3）使用方法，ISE版本为13.1-MIG user guide
rdf0011
- 用VerilogHDL遍写的ddr3控制器，使用了自带的ip核生成mig来进行读写。-Times to write with VerilogHDL ddr3 controller, use the ip core generator that comes with mig to read and write.
ddr3_advantages1
- 详细介绍ddr3 ram的优势!可以为设计者提供一个很好的帮助-Details the advantages of DDR3 ram
emi(1)
- the external memory interface for the ddr ddr2 ddr3 sdram device
source
- altera DDR3 逻辑测试代码，这是工程实际调试好的代码，保证能用。-altera DDR3 vhdl code
JESD79-3E
- This document provides implementation instructions for the DDR3 interface-This document defines the DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this
xapp741
- xilinx视频处理包示例，包括VDMA，VTC，DDR3控制等。-Xilinx video processing package example, including VDMA VTC, DDR3 control, and so on.
ddr3_12.1V
- DDR3 Simulation environment
ml605_MIG_rdf0011_13.4_c
- 该参考程序是基于xilinx ml605开发板的一个DDR3参考设计，源文件包含相应的管脚约束文件。-The reference procedure is based on xilinx ml605 development board a DDR3 reference design source file contains the corresponding pin constraint file.
vc707-mig-rdf0160-14.3
- 适用于DDR3 控制器代码等的FPGA代码-DDR3 controller code for FPGA code, etc.
DDR3__Layout_Design
- DDR3的layout指南，硬件工程师必备-Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces
ddr3_mcb1
- 基于SPARTAN 6 的DDR3的实现。-The Verilog code for DDR3 on the SPARTAN 6
PCIE_DMA_DDR3_verilog_design
- 基于xilinx fpga的pci-e到dma再到ddr3的数据传输完整设计-PCIE_DMA_DDR3 verilog reference design
ddr
- davinci平台dm8168外接DDR3功能测试-davinci dm8168 external DDR3 functional test platform
DDRController
- DDR3控制器，用于FPGA内部对DDR进行操作，利用Avlone总线进行对接-DDR controller
ddr3_uniphy_siv_example_restored
- A system that is written in Verilog to be able to read and write data to a DDR3 RAM by Altera FPGA