搜索资源列表
fpga
- 这是一个利用verilog HDL语言编写的自动频率计设计项目，能运行-This is a verilog HDL language automatic frequency meter design projects, and be able to run
Verilogpinlvji
- 基于verilog HDL的频率计设计，多个模块，误差较小。-Based on the the verilog HDL frequency meter design, multiple modules, the error is smaller.
Motor.asm
- 基于verilog HDL步进电机驱动程序-The verilog HDL stepper motor driver
HDB3编解码器课程设计
- 对HDB3码型基本原理和特性的认识、对Quartus Ⅱ软件的熟练操作、对Verilog HDL的掌握和应用，这些知识都是进行电子设计的基本知识和能力，只有基础知识和能力扎实了，才能更好的进行更高层次的电子设计，所以这个设计也是对电子设计基本能力的很好的锻练。
hdl-v3a
- VHDL coding tutorial with examples PPT
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
lab-4-cpu-design-with-Verilog-HDL
- 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
jiaozhi
- 完成通信系统中数据交织器的设计的设计，要求用Verilog HDL编程，包括源程序，仿真波形和实验结果及分析结论等。 -Completed the design of the communication system data interleaver design requirements using Verilog HDL programming, including source code, simulation waveforms and experimental results an
verilog-uart
- UART（Universal Asynchronous Receiver Transmitter，通用异步收发器）是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路，分析UART的传输时序并利用Verilog HDL语言进行建模与仿真，最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive
soft
- xhdl is a software about hdl.
Principles-of-Verifiable-RTL-Design
- 本书主要以HDL（verilog/vhdl）为例，详细讲述了在IC DESIGN FLOW中 Verification 以及Test的设计思想、方法和技巧，涵概了测试的各个方面， 是目前进行IC设计的同仁们最为推荐的一本宝典-(Kluwer) Principles of Verifiable RTL Design (2nd Ed.)
rmii
- rmii 以太网接口时序源代码，值得开发借鉴的哦-verilog hdl
ht_fifo
- fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
crc32
- crc-32 主要用于网络传输中的 检测，防止错误数据传输-verilog hdl
MOTOROLA-Verilog-HDL-Coding-standard
- 文档是关于verilogHDL的代码规范的，编写方是MOTOROLA，对于规范VerilogHDL格式有借鉴意义-Document is about verilogHDL code specification, the preparation side is MOTOROLA, VerilogHDL format for standardizing reference
shixunlaozhong
- 基于Verilog HDL语言的多功能数字钟，能够实现置位和清零功能。 -Verilog HDL language-based multi-function digital clock, to achieve set and clear functions.
src
- Concatenator for calculator synthesizable in verilog hdl.-Concatenator for calculator synthesizable in verilog hdl.
Verilog-HDL
- 给出了学习verilog心得，其中包含了典型的代码例子，适合初学入门。-verilog program demo and method.
light-control
- ABEL-HDL语言编写的八路彩灯控制器（三种花型）-ABEL-HDL language of the eight lantern controller (three kinds of flowers)
rs_code
- 本文在介绍卷积码原理和描述方式的基础上以1/2卷积码为例重点详细阐述了基于Verilog HDL 的卷积码的编器的设计-This paper introduced the convolution code on the principles and methods described in 1/2 convolutional code as an example focuses elaborated convolution based on Verilog HDL code compiled