搜索资源列表
DCT
- altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim 验证，文件中包含TESTBENCH ，直接可用
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
VHDL_Testbench
- Altera官方的VHDL_Testbench教程,想学怎么写Testbench的话,强烈建议看一看。（英文的文档，不过都不难。耐心看完吧！）-Altera official VHDL_Testbench tutorial, want to learn how to write Testbench, then strongly recommended that a look. (English document, but are not difficult. The patience to re
cordic_generic
- 本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法，并且在原始的级联型的基础上编写的循环(iterative)型的cordic,可通过generic配置。带一个不可综合和可综合的testbench(for altera)。稍微改动可应用于xilinx fpga-a generic synthesizable cordic with 2 modes: cascade and iterative. based on opencores.org version,
cordic
- altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
testbench
- altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。-altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.
get-start-with-modulesim
- 内含基于altera公司的FPGA芯片用modulesim仿真步骤，和详细实例，教会怎么使用modulesim仿真和编写testbench程序。-Altera FPGA-based embedded chip company with modulesim simulation steps, and detailed examples, how to use the church modulesim testbench simulation and preparation procedures.
nco_tb
- nco的测试文件，基于altera的nco核的测试程序-nco_td altera ip core testbench
rgb2yuv
- 在Altera的开发环境上，用Verilog语言实现的RGB转YUV，附有Testbench-In Altera s development environment, using Verilog language of RGB to YUV, with a Testbench
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
Example-b8-1
- 使用ModelSim对Altera设计进行功能仿真的简要操作步骤 1.建立仿真工程 2.Altera仿真库的编译与映射 3.编译HDL源代码和Testbench 4.启动仿真器并加载设计顶层 5.打开观测窗口，添加信号 6.执行仿真-Using ModelSim Altera design for functional simulation brief Procedure 1. Create a simulation project Compilation and map
Example-b8-2
- 使用ModelSim对Altera设计进行时序仿真的简要操作步骤 1.建立工程，设置仿真工具选项参数 2.使用Quartus II编译工程 3.建立仿真工程 4.Altera仿真库的编译与映射 5.编译HDL源代码和Testbench 6.启动仿真器并加载设计顶层 7.打开观测窗口，添加信号 8.执行仿真-Using ModelSim Altera design for timing simulation of brief steps 1. Establish pro
TEXIO
- TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus
gray_counter
- altera官方格雷码计数器的verilog代码和testbench,已测试-altera official Gray code counter verilog code and testbench, have been tested
fpga
- 有关FPGA的好多资料的综合汇总，包括夏宇闻-Verilog经典教程，Verilog-testbench的写法，Altera+FPGA／CPLD设计高级篇，Altera+FPGA／CPLD设计基础篇等好几本书，超值-A comprehensive summary of a lot of information about FPGA, including Xia Wen-Verilog classic tutorial, Verilog-testbench writing, senior Alte