搜索资源列表
fnpll
- 小数分频PLL的matlab源代码，包含二阶sigma-delta调制器的源码。-Fractional PLL the matlab source code
NdotXfd
- 小数分频，可以实现任意小数的分频，基于VHDL程序- it was verygood， yes ，it was。yeah ，it can be very important thing
digitalfreq
- 由于本人没有多少很好的源码，所以只能上传目前所做项目的相关参考文献资料。资料一的内容是数字分频器的参考文献，在fpga中数字分频器用的很多，文献对于设计小数分频器有一定的参考价值。-I am not much good as the source, we can only upload now doing projects related reference materials. Information content of a digital divider references in the
div_fru
- 介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。-Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not
frenquent
- 分频器的一些程序。包括整数分频，小数分频，我感觉非常好的资料，不敢私自分享。特拿出来分享。希望想学习的好好参考下，肯定会有所感悟。-Divider of some procedures. Including the integer frequency, fractional, and I feel very good information, not privately share. Point out to share. They want to study more carefully th
VHDL_fre_div
- 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of ex
fenpin
- 分频电路的研究 主要包括：偶数分频（二分频、偶数分频占空比50 ）、奇数分频（占空比50 、占空比非50 ）、半整数分频（不要求占空比）、小数分频（不要求占空比）。 -Frequency of the circuit includes: an even frequency (half frequency, frequency 50 duty cycle even), odd-frequency (50 duty cycle, duty cycle of non-50 ), half-
FPGA-DEVIDER
- 基于FPGA的小数分频器的实现 频率合成技术是现代通讯系统的重要组成部分,他将一个高稳定和高准确度的基准频率,经过四则运算,产生同样稳定度和基准度的频率。-FPGA-based implementation of the fractional divider frequency synthesis technology is an important component of modern communications systems, he has a high stability and
FPGAxiaoshufenpin
- 实现任意分频的分频器设计，包括小数分频，任意小数分频的设计方案-ren yi xiao shu fen pin
pll
- 基于simulink的频率合成器实现，可实现小数分频-Simulink-based frequency synthesizer implemented to achieve fractional
vhdl
- 任意数分频程序，包括小数分频，任意占空比奇数，偶数分频-Arbitrary number of frequency programs, including fractional, any duty cycle odd, even frequency
SingleLoopSDM_prj
- 对频率综合器中的小数分频器进行优化配置，减小参考杂散。-Of the fractional frequency divider in the synthesizer to optimize the configuration, reducing the reference spur.
GetKey
- cpld的按键处理，偶数分数，奇数分频，小数分频-cpld key handling, even scores the odd frequency, fractional-N
fp_del
- 脉冲删除法实现任意小数分频，缺点是占空比不可调-Pulse delete method to achieve any fractional frequency, duty drawback is not adjustable
fp_3
- 同样是实现任意小数分频的Verilog程序，但采用了模块化地方法，占空比可调。-The same is to achieve any fractional frequency of the Verilog program, but to use a modular approach, variable duty cycle.
fp_top
- 在任意小数分频程序中加入了UART接收模块，可以接收分频系数并实现分频。-In any fractional program joined the UART receiver module can receive the frequency factor and achieve frequency.