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yh2
- 基于VHDL语言，应用于偶数或者奇数的小数分频-failed to translate
fenpin_m
- 基于VHDL的一种小数分频器，能够实现任意的小数分频-A decimal frequency divider base on VHDL, be able to achieve any decimal frequency divider
DIV_oddN
- Quartus开发环境下，通用小数分频器的设计，满足各种需求。-Quartus development environment, the design of the universal fractional divider, to meet various needs.
fenpin11
- 该小数分频器利用VHDL语言，在同一程序中实现了分频比交错、累加器分频两种方式。采用同步时序。-The decimal prescaler use VHDL language, in the same procedure to realization of points staggered, frequency than accumulators points frequency in two ways. The timing synchronization.
any-fre
- 任意分频，小数分频，计数分频的源代码，直接使用的模块，，已经在开发中使用过的IP包-Any frequency, fractional frequency count divided by the source code
four_five
- FPGA的VERILOG的小数分频，可以对任意小数分频，准确-FPGA is good for your study of your verilog langer
qaa
- 任意小数分频器，可以实现小数分配，非常好用，verilog编写-Any decimal prescaler, can realize the decimal distribution, is very nice verilog writing
clk_div
- 介绍了一种基于FPGA的小数分频器的分频原理及电路设计- decimal frequency divider based on FPGA
VHDL-divider-design
- VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-cr
VHDL-fen-pin
- VHDL分频器，普通分频，偶数分频，奇数分频，小数分频等各种分频器的编写-The preparation of the VHDL divider, sub-frequency, even frequency, odd division, fractional-N divider
divider
- 偶数 奇数 小数分频器的设计,很详细实用，希望对大家有帮助-even odd frequency_divider
xiaoshu
- 基于Verilog的小数分频,带testbench，可直接modelsim仿真-Verilog-based fractional divider with testbench, modelsim simulation can be directly
fen-pin-Verilog(2013-06-25-09.54.41)
- 任意小数分频，适用于对精确度要求不高的代码中-Any fractional divider, suitable for less demanding precision code
division
- 分频器,偶数分频 奇数分频 小数分频 不同方法实现不同种类分频 -Divider, even odd frequency divider fractional different ways to achieve different types of crossover
Half_Frequence
- 本程序基于VHDL语言，设计分频器，其中包含半整数分频占空比不为50 奇数分频占空比为50 任意小数分频 -The program is based on VHDL language design divider, which includes half-integer divider 50 duty cycle is not odd frequency 50 duty cycle any fractional
GetKey
- cpld的按键处理，偶数分数，奇数分频，小数分频-cpld key handling, even scores the odd frequency, fractional-N
Prescaler-to-use-VHDL-design
- 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。-This paper describes the use of examples prescaler to use VHDL design on FPGA/CPLD, i
pll_sigma-delta
- 这是用simulink仿真的一个小数分频锁相环（fraction_N PLL），使用了sigma-delta modulator和8/9预分频，这只是其中一部分，如果再想实现细节，还有待更深入，可以联系我qq790290115-fraction_N PLL using simulink(2013a),it includes sigma-delta modulator and 8/9 prescaler
fenpin
- 分频程序，偶数分频，奇数分频，占空比可调，小数分频-Dividing frequency division program, even, odd points frequency, duty cycle adjustable, the decimal frequency division
clk_generator
- 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files