搜索资源列表
mult
- 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
verilog
- verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
multiplier.tar
- 用vhdl实现的booth算法乘法器，包含了multiplexer和rca adder，同时提供了一个测试文件，modelsim测试通过-Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass
VHDL-test-codeBooth-multiplier
- VHDL实验代码：Booth乘法器，是一个基于VHDL语言开发的程序，非常的实用-VHDL test code: Booth multiplier, is a VHDL-based language development program, a very practical
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
lamao
- 用拉格朗日乘子法求解约束最优化问题，很好的实例程序。-Lagrange multiplier method for solving constrained optimization problems, very good example programs.
booth
- 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
32_bit_complex_multiplier
- 一款32位复数乘法器，用verilog写的。-32_bit complex multiplier,written in verilog HDL.
array_multiplier
- 4X4阵列乘法器，图可以按程序画看看，可以改进-4X4 array multiplier, see Figure can draw according to the procedure can improve
multiplier
- 4 bit ordinary multiplier
CCMU
- 代码是一个复数乘法器，两个复数相乘，只用到了2个实数相乘，运算量少-Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less
cmultip
- 用VERILOG HDL 实现节省乘法器的16位复数乘法器-With VERILOG HDL achieve savings of 16-bit complex multiplier multiplier
DCM
- Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for
multiplexer
- 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
32-bit_multiplier_model
- 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
cmult
- 复乘法器的FPGA实现， 希望对初学者有帮助 -Complex Multiplier FPGA to achieve, and they hope to help beginners
multi16
- verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
GFmultiply
- Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
Wallace
- 一个关于Wallace树乘法器的论文，当中展示了一种改进后的wallace树乘法器方案，相比原来占用晶体管更少，效率更高-Wallace tree multiplier on the papers, which show an improved wallace tree multiplier after the program, compared to the original transistors occupy less efficient
fir_parall
- 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu