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signed four bit multiplier
- a multiplier for four bit binary number
mulf2m.rar
- 椭圆曲线加密算法中的乘法器的生成，主要功能是实现在素域上的多项式模P(大素数）乘的运算。,Elliptic curve encryption algorithm to generate the multiplier, the main function is to achieve in the Su-domain polynomial module P (large prime numbers) by the operator.
Multiplier.rar
- 乘法器 所占资源很少 很好的一个乘法器 史书上的一个例子 说得很好啊,Multiplier good share of scarce resources in the history books on a multiplier an example of very good
32bit.zip
- multiplier and divider verilog codes,multiplier and divider verilog codes
booth.rar
- 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码,VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
optimizationinMatlab.rar
- MATLAB最优化计算20例.m文件，包括二次插值，黄金分割，罚函数法，遗传算法，拉格朗日乘子法等,MATLAB Optimization Calculation of 20 cases. M documents, including quadratic interpolation, Golden Section, penalty function method, genetic algorithm, Lagrange multiplier method
booth_multiplier
- Booth multiplier written in verilog
rpca
- RobustPCA 是最近提出的一种非常新的图像矩阵分解算法，该算法具有对噪声不敏感、能处理高维图像数据的特点。这是论文作者提供的 MATLAB 实现代码。-Oct 2009 This matlab code implements the augmented Lagrange multiplier method for Robust PCA.
mux4
- 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic descr iption of
mult_piped_8x8
- 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
multiplier-accumulator(vhdl)
- 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of
8-bit-Multiplier
- 一种基于加法器树方法的8为乘法器的VHDL源码，该方法虽然相对占有资源多，但仿真快-VHDLSourceProgramof8-bit-Multiplier
Multiplier
- BJ-EPM240V2实验例程以及说明文档实验之五乘法器设计-BJ-EPM240V2 experimental test routines as well as documentation of the five multiplier design
multiplier
- 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplica
Multiplier
- It s a design of a 4*4 multiplier based on Verilog, using Xilinx ISE.
floating-point-multiplier
- verilog implementation of the floating point multiplier
Multiplier
- 时序乘法器，verilog编写，速度慢，但消耗资源少，时钟沿到来时，输入/输出1bit数据-Sequential multiplier, verilog written, slow, but consume fewer resources, the clock edge arrives, the input/output 1bit data
PARALLEL-MULTIPLIER
- vhdl code for a 32 bit parallel multiplier
jeas_reversable-vedic-multiplier
- reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output
binary multiplier
- verilog code for binary multiplier