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leijiaqi
- verilog 语言描述的累加器和乘法器-verilog code
challenge-receive
- 飞思卡尔MC9S12XS128 脉冲累加器使用-Freescale MC9S12XS128 pulse accumulator
multi_booth
- verilog编写的booth算法的8x16乘法累加器-verilog prepared booth algorithm 8x16 multiplier-accumulator
Hough--transformed
- 利用图像空间和Hough参数空间的点－线对偶性，把图像空间中的检测问题转换到参数空间。通过在参数空间里进行简单的累加统计，然后在Hough参数空间寻找累加器峰值的方法检测直线。-Use of image space and Hough parameter space point- line duality theorem, the detection problems in image space transformation to the parameter space. Through si
1.5Accumulator
- 累加器，由mux，register，adder组成的n ；bit累加器-Accumulator, the mux, register, adder composed of n bit accumulator
Add_ahead
- 无流水线加法器与寄存器结合在一起的相位累加器设计程序-vhdl implementation of phase accumulator without pipelines
ImprovePipelineAdder
- 基于流水线加法器与寄存器结合在一起的相位累加器设计程序-vhdl implementation of phase accumulator with pipeline and registers.
PipleFullAdder
- 基于流水线的超前进位相位累加器设计程序,速度明显优于无流水线超前进位累加器-vhdl implementation of phase accumulator with pipeline and advanced carry.
999leijia
- 在C语言的环境下，利用单片机产生一个累加器的信号，希望对大家有用。-In the C language environment, using SCM accumulator generates a signal, we want to be useful.
fir18
- 介绍了一种基于FPGA和高精度A/D转换器结合的FIR滤波器电路系统,该滤波器采用乘法累加器算法,并利用X ilinx公司XC3S500E的FPGA进行试验验证,主要包括对输入的正弦波信号进行A/D转换后进行滤波,通过上位机显示滤波结果。 -Introduces an FPGA-based FIR filter circuit systems and high-precision A/D converter combined, the filter algorithm using multipl
houghbianhuan
- hough变换，matlab编程。Hough变换是一种使用表决原理的参数估计技术。其原理是利用图像空间和Hough参数空间的点－线对偶性，把图像空间中的检测问题转换到参数空间。通过在参数空间里进行简单的累加统计，然后在Hough参数空间寻找累加器峰值的方法检测直线。-hough transform, matlab programming. Hough transform is a vote on the principle of using a parameter estimation tech
my_multiplier
- 一个VHDL编的简单乘法器，基本原理设计如下图所示: 将两个操作数分别以串行和并行模式输入到乘法器的输入端, 用串行输入操作数的每一位依次去乘并行输入的操作数, 每次的结果称之为部分积, 将每次相乘得到的部分积加到累加器里, 形成部分和, 部分和在与下一个部分积相加前要进行移位操作。-A simple multiplier VHDL series, the basic principles of design as follows: two operands, respectively, ser
DDS
- DDS的核心是相位累加器，相位累加器有一个累加器和相位寄存器组成，它的作用是再基准时钟源的作用下进行线性累加，当产生溢出时便完成一个周期，即DDS的一个频率周期。加载Matlab 产生的波形，通过FPGA输出DDS信号-Core DDS is the phase accumulator, a phase accumulator and phase accumulator registers, its role is to carry out a linear accumulation under
half_band
- 半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考-Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference
123455
- 32位累加器，包括32位加法器与寄存器，程序与仿真文件包含在内，在相应的环境下可直接运行-32-bit accumulator, including 32-bit adder and register, procedures and simulation files included, can be run directly under the corresponding environment
NCO
- 基于FPGA的DDS设计，通过外接DA转换器输出稳定的正弦波，方波和三角波，可单独产生时钟，不必借助硬件连接，包含寄存器程序，累加器程序和时钟发生电路等，以及顶层设计原理图-The DDS FPGA-based design, through an external DA converter output stable sine wave, square wave and triangular wave, can produce a single clock, without the help
counter
- FPGA编程，用Verilog语言实现4位累加器功能-The FPGA programming, realize four accumulator with Verilog language features
s5
- 清华大学电子系 时序逻辑实验报告 包括：触发器设计，计数器设计，累加器设计，序列检测器设计/有限状态机实现-Tsinghua University, Department of Electronics, sequential logic test report include: trigger design, counter design, accumulator design, the sequence detector design/finite state machine
add_sin
- 使用quartus软件编写VHDL语言一个累加器程序-Quartus software using VHDL language to write a program accumulator
Private-Sub-Command1
- 数字累加器，可键盘输入，也可鼠标操作。是初学者的练习，不要见笑了-Digital accumulator keyboard input, but also the mouse. A beginner' s exercise, do not laugh at the