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add1A
- 用于实现锁相光子计数技术的累加器，verilog语言-Accumulator achieve specific cases for accumulator lock detection of photon counting technique
leijia
- 用LabView制作出来的累加器，可以对数进行累加-Using LabView, made an accumulator can be cumulative logarithmic
pipeline_add
- pipeline式累加器的verilog代码和testbench文件，已验证-pipeline type accumulator verilog testbench code and documents, verified
sin_en
- DDS 由相位增量器，相位累加器，量化器以及正余弦查找表四部分组成。 相位累加器每一周期会累加上固定的相位值，然后从查找表中找到对应的数值。-DDS by the phase increment, phase accumulator, quantizer and sine and cosine lookup table of four parts. The phase accumulator accumulates a fixed phase value for each period,
TIM
- 飞思卡儿 计时器time 的脉冲累加器产生原理的例子，已经测试通过。-Freescale timer time pulse accumulator produces an example of the principle that has been tested.
eda
- 直接数字频率 相位累加器 寄存器 lpm_rom(Based on VHDL+ FPGA design of the DDS signal has been through mode)
hough
- 对图像进行霍夫变换检测直线。遍历图像，把极坐标下点转换到霍夫空间，同时累加器加1，最后统计累加器数组中的极大值点，便对应原图中的直线。(The image is transformed by Hof transform to detect the straight line. Traverse the image, transform the point in polar coordinates to Hof space, accumulate 1 at the same time, and f
15010120041_高瑞雪_lab2
- 在本实验中，将使用System Generator for DSP创建一个带乘法器和累加器的12-bit x 8-bit MAC（Multiplier Accumulator），并使用System Generator 的Resource Estimator块来估计资源利用率。 在仿真Simulink中的设计之后，将从该设计中生成VHDL代码和内核，并在Xilinx ISE Foundation开发软件中实现MAC。(Design, construct and verify the specifi
sumexp
- e是输入，sum_e是输出，cnt_in是累加数据的个数。这个模块是我（新手）一个项目中用来累加exp(x)的一个模块。(E is the input, the sum_e is the output, and the cnt_in is the number of accumulative data. This module is a module that is used to add exp (x) to a project in my (novice) project.)
dds_rom
- 基于查找表的DDS的Verilog实现，分为相位累加器模块、ROM模块和顶层DDS模块(Verilog implementation of DDS based on lookup table)
pb_lx
- 功能：w_1向w_2传参(累加次数)并触发w_2控件cb_1(累加器)；w_2控件cb_1计算从1至所接收累加次数的累加值并返回w_1。 目的：说明窗口间相互触发控件及传参、传值的技术细节。(Function: w_1 passes to w_2 (accumulating times) and triggers w_2 control cb_1 (accumulator); w_2 control cb_1 calculates accumulative value from 1 to re