资源列表
VisualDSPPP4.0_getting_started
- Visual DSP++ 4.0开发软件的操作手册和详细说明，英文的。-The operating manual of Visual DSP 4.0 and a detailed descr iption of Visual DSP++ 4.0 development software, operating manuals and detailed instructions in English.
VHDL-based-curriculum-design
- 基于VHDL实现的电子琴课程设计 VHDL-based curriculum design to achieve the keyboard-VHDL-based curriculum design to achieve the keyboard
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
work1
- （1）编写程序,产生NTSC彩条信号(ITU-R656格式),并通过实验板(ADSP-BF533 EZ-KIT)的视频输出口,输出到电视监视器上。 （2）编写程序，将一图片(720x486)输出到电视监视器上。 -(1) programming, resulting in NTSC color bar signal (ITU-R656 format), and through experimental board (ADSP-BF533 EZ-KIT) video output, out
Final_Belajar
- VB.Net hotel reservation application. Simple program but very good basic for you who wants to develop it further.
FSM
- 一个简单的有限状态机(FSM)的例程：检测二进制序列“11001”-A simple FSM routines: testing the binary sequence "11001"
VHDL-music-autoplay
- 基于VHDL实现的梁祝自动乐曲播放器，欢迎大家下载-VHDL-based implementation of the Butterfly Lovers automatic music players, are welcome to download
Excise4
- 编写程序,读出实验板(ADSP-BF533 EZ-KIT)上Flash A存储器中的图像数据, 变换成ITU-R656 NTSC格式后输出到电视监视器上。-Programming, read the test board (ADSP-BF533 EZ-KIT) on the Flash A memory image data, converted into ITU-R656 NTSC format output to a TV monitor.
Excise05
- 编写程序,读出实验板(ADSP-BF533 EZ-KIT)上的Flash存储器中的图像数据, 变换成ITU-R656 NTSC格式后输出到电视监视器上,并且可以用按键切换图像显示，按键按下的同时要求LED指示灯亮一下。-Programming, read the test board (ADSP-BF533 EZ-KIT) in the Flash memory on the image data, converted into ITU-R656 NTSC format output to a
ta
- 键盘钢琴，比普通的键盘钢琴更近一步，实现更多功能-Keyboard, piano, piano keyboard than normal step closer, more functions
verilog
- Verilog学习例程：4位二进制数的乘法器、5分频器、8位数据寄存器、8位移位寄存器、边沿D触发起门级设计、边沿D触发器行为级设计、同步计数器、异步计数器-Verilog learning routines: 4-bit binary number multiplier, 5 dividers, 8-bit data registers, 8-bit shift register, edge-triggered D gate-level design, level design edge D
VHDL-Multiplier
- 资料是EDA的一个课程设计，基于VHDL实现的乘法器，包含论文，欢迎下载-EDA data is a course designed to achieve a multiplier based on VHDL, including paper, please download