资源列表
eda_traffic_light
- vhdl实现交通灯设计,可以实现十字路口处交通控制,开发工具quartus-vhdl traffic lights to achieve the design, can be achieved at a crossroads Traffic Control Office, Development Tools quartus
send_cmd
- SD card SDIO module send command and read response
dongtaishumaguan
- 用verilog HDL编写的基于fpga的动态数码管显示程序。-Verilog HDL prepared with fpga based digital control of dynamic display program.
lift
- 我自己写的六层电梯程序，用的语言是VHDL，还有仿真的图，非常有用，-I wrote it myself six lift procedures, the language used is VHDL, simulation of the Fig also, very useful,
VHDL
- 上海交通大学VHDL课程的所有作业代码，欢迎有需要的XDXM光顾-homework of VHDL course at SJTU
vhdl
- vhdl学习必看书籍。绝对经典的好书 -learning vhdl book a must-see. Absolute classic books
manchester_verilog
- 用verilog写的一个manchester code的代码，含编解码-Used to write a verilog code for manchester code containing codec
rom
- 只读存储器VHDL代码，可运行实现，已用quartusII6.0验证-Read-only memory VHDL code can be run to achieve has been used to verify quartusII6.0
Revised_Verilog_code
- 简弘伦：Verilog HDL IC设计核心技术实例详解 源代码,更新版本-Honglun Jian, Revised Edition. Source coude of " Core Techniques of IC design"
wodeshji
- 在FPGA上，实现了一个多功能数字抢答器，设置四个抢答按钮，及若干控制台按钮，有计分，抢答，重置，及时等功能-In the FPGA, the realization of a multi-functional digital Answer, and set up four Answer button, and a number of console button, there are points, Answer, replacement, and other functions in tim
timing_constraint
- 主要介绍xilinxFPGA时序约束的方法和技巧。FPGA开发人员进一步提高的必看资料。-XilinxFPGA timing constraints introduces methods and techniques. FPGA developers to further enhance the information of the must-see.
ADC
- verilog code for ADC