资源列表
AHBtoAPB.rar
- amba总线桥:ahb to asb!verilog hdl文档加代码，非常全，soc,amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc
vhdl
- 本设计中应用硬件描述语言Verilog HDL描述相位累加器，相位调制器，正弦波、方波、三角波、心电波形四个独立的波形存储器，并描述频率控制、相位控字、幅度控制单元及波形切换等相关的功能单元。-Application of the design described in Verilog HDL hardware descr iption language phase accumulator, phase modulator, sine, square, triangle wave, the fo
DDS
- 用Verilog编写的DDS逻辑,很好地实现了DDS功能，可以产生各种频率的正弦波。-DDS which was write by Verilog。
2point_data
- 基于Quatusii的两点非均匀性校正的VHDL程序，用于红外图像的预处理-Quatusii based on two non-uniformity correction in the VHDL program for infrared image preprocessing
config_ad9957
- 用Verilog正确配置ad9957，，在ISE环境中正确编译与实现-Properly configured with the Verilog ad9957,, compiled in the ISE environment and realization of the right
SATA_Verification_IP-SystemVerilog
- SATA Verification IP - SystemVerilog,是使用FPGA做的sata接口部分，是一篇文档-SATA Verification IP- SystemVerilog, is to use FPGA to do sata interface part, is a document
FPGA
- 基于FPGA设计的多功能信号发生器，可以生成各种常用的波形-FPGA-based design of multi-function signal generator, can generate waveforms of various commonly used
mcode
- 用VHDL语言生成m序列，进行扩频。m序列是10级的。-m sequence
AD8522_SPI
- AD8522模拟数字转换芯片sdi接口配置代码-AD8522 analog-digital converter chip sdi interface configuration code
Quartus_II_7.2_b151破解器
- Quartus_II_7.2_b151破解器.用于Quartus_II_7.2,Crack Quartus_II_7.2_b151 browser. For Quartus_II_7.2
使用verilog hdl实现16位的cpu设计
- 实现16位的cpu设计 内容使用verilog hdl实现，具体的实现步骤方法，都已经写到文档里面去了！,To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
DM642.rar
- 和众达DM642EVM上FPGA内的程序！,And public DM642EVM Tatsu procedures on FPGA!