资源列表
FPGA_verilog_uart-
- 基于 FPGA器件设计实现UART的波特率产生器、UART发送器和接收器及其整合电路,，利用Veriolog-HDL语言对这三个功能模块进行描述并加以整合，通过ModelSim仿真，用串口调试程序进行验证，最终实现一个通用异步收发器的设计。-UART baudrate generator, transmitter and receiver and its integrated circuit are implemented by FPGA device. Using Veriolog-HDL d
kss
- 可以加载歌曲，然后可以播放，暂停，停止，下一曲，单曲循环等功能。-Can load a song, and then you can play, pause, stop, under a single cycle.
paper
- 这是计算机科学与技术专业ASP.NET课程设计关于二级报名系统的课程设计报告-Computer Science and Technology Professional ASP.NET curriculum design curriculum design report on the two registration system
Board.ALtera FPGA Cyclone III开发电路图
- ALtera FPGA Cyclone III开发电路图，对初学者设计此类FPGA有重要参考价值,ALtera FPGA Cyclone III development of schematics, such FPGA design for beginners have important reference value
SPWM-wave-DSP-control-algorithm
- 正弦脉宽调制(SPWM)波的DSP控制算法的PPT讲义，也是毕设答辩时的PPT内容-Sinusoidal pulse width modulation (SPWM) wave DSP control algorithms PPT handouts, but also completed the set contents of the PPT reply
xcalc
- 小型计算器，绝对经典。 MFC初学者必看。-Small calculator, absolute classic. MFC beginners must see.
KLD
- kld采样算法的c语言实现，需要在linux环境下面运行-kld sampling method for c language, you need to run under linux environment
tktktk
- 从同学哪里拷贝来的程序,毕业设计用的,大家看看,有帮助的哦-where copy from classmates to the procedure, a graduate of the design, we look at the help oh
LiveUpdate
- 这是针对第三方启动而设计的软件更新下载软件，实习远程更新文件下载和版本的更新，配置文件的读取操作等。
MarketSMS_v2.2
- send SMS, RECIVE sms, application for windows
LCD_CLOCK
- 用1602液晶显示的数字电子钟，并且可以用按键开关调整时间，日期，星期。-1602 LCD display with digital electronic clock, and the key switch can be used to adjust the time, date, week.
AM_Segmentation
- thése de segmentation des images