资源列表
ring
- 使用VRML的extrution节点和教本编写的画环扩展节点-use VRML extrution nodes and textbook prepared by the Central painting expansion joints
gauss_noise_edgedetection
- 在VC环境中具有高斯噪声的情况下图像处理边缘检测源代码，效果不错的。-in VC environment with Gaussian noise of image processing Edge Detection source code, the effect is not too bad.
sell
- 基于FPGA的自动售饮料机，包含2.5元、3元两种选择-FPGA-based beverage vending machines, including 2.5, 3 yuan two options
fsmd_debounce_exp
- vhdl debounce circuit
VHDL-test-code-general-register
- VHDL实验代码：通用寄存器组，这是一个基于VHDL开发的程序，非常的实用-VHDL test code: general register, which is a VHDL-based development process, a very practical
Digital-Clock
- FPGA数字跑表代码 Digital Clock-Digital Clock
PWM
- 循迹小车PWM电机c语言程序，可以控制小车的转弯与行走。-failed to translate
B_spline
- 用最简单的matlab程序实现B-Spline曲线的绘制-B-Spline curve drawn with the most simple matlab program
SDRAMping-pong-memory-structure
- 双口RAM 的乒乓存储结构（芯片型号CY7C09279） 应用场合为FPGA向双口RAM不断写入数据，PCI总线从RAM读取数据。[已调试验证]-Dual-port RAM, ping-pong memory structure (chip model CY7C09279) applications for the FPGA to the dual-port RAM write data continuously, PCI bus read data from RAM. [Debugging
AppletImg
- java applet show image
firtesmul
- 基于FPGA的FIR滤波器实现，并行乘法实现，运行速率快但占用资源多。-FPGA-based FIR filter, parallel multiplication achieve faster run rate but take up more resources.
CLOCK-CODE-VHDL
- VHDL源码程序，功能完整的时钟电路代码-using ALTERA s FPGA design, QUARTUS software development platform.VHDL CARD,