资源列表
project48
- 单片机采用中断方式，对2路0-5V的模拟电压进行循环采集，采集的数据送LED交替显示，并存入内存。超过界限时指示灯闪烁。（哈工大单片机大作业内附proteus原理图）-Microcontroller interrupt loop acquisition of 2-way 0-5V analog voltage data collected to send the LED alternately displayed and stored in the memory. Indicator flash
Based-FPGA-digital-clock-design
- 基于FPGA的数字时钟设计，这里是我做的一个电子时钟，大家可以借鉴一下！-Based FPGA digital clock design
xilinx-ise-13.1-operation-flow
- 此文档介绍了如何在xilinx ise 13.3的开发环境里面进行开发，并将程序下载到xilinx fpga里面-This document describes how to development, and download the program to the inside of xilinx fpga xilinx ise 13.3 development environment inside
divider
- divider 这个程序是教你如何写一个偶数的分频器，用它可以完成任意进制偶数分频器-divider of this program is to teach you how to write an even divider, you can use it to complete any hex even-numbered divider
Working-principle-of-FPGA-
- 此文档详细的说明了fpga的工作原理和结构，看完了之后会对fpga有了一个很深的了解-This document is a detailed descr iption of the working principle and structure of fpga be fpga With a deep understanding after reading the
dingshizhongduan
- 51单片机汇编实现定时中断，使用多个计时器和中断器-The 51 MCU compilation timer interrupt use more than one timer and interrupt controller
51qiangdaqi
- 51 控制的抢答器 内涵protues仿真电路
bitmap
- bitmap实现，C语言实现，在linux内核里边找的-bitmap realize the C language, and find linux kernel inside
VB-AVR
- VB程序实现与AVR单片机的通讯，来控制单片机的IO。-VB communication with avr
CPLD-code
- CPLD开发板实验代码，包括Verilog和VHDL源代码，原理图-CPLD development board experimental code, including Verilog and VHDL source code, schematics
verilog-ip-core
- verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
evm6424_audio
- EVM6424上音频接口编程示例，希望对需要的人有所帮助，经过CCS3.3验证-EVM6424 on the audio interface programming examples, I hope to help people in need, after CCS3.3 verification