资源列表
xapp870
- xilinx v5上sata link 初始化文档-Xilinx Sata link initilization guide
i8255_verilog
- 8255的Verilog hdl源代码，适合FPGA工程师使用-8255' s Verilog hdl source code for FPGA engineers
LVDS
- 高速串行差分接口（HSDI）设计实例,用QUARTUS和利用FPGA实现LVDS的方法。-High-speed serial differential interfaces (HSDI) design example implementation using FPGA LVDS QUARTUS and use of the method.
de2-sd-mp3player
- de2板上，先存入sd卡，实现的MP3播放器功能-de2，sd2，MP3player
DE2_i2sound-g5
- 通过de2板上的wm8731，42阶音量可调，mic和dac同时输出。-By de2 board wm8731, 42 stage adjustable volume, mic and dac output simultaneously.
CCD-driver
- CCD芯片驱动VHDL程序，CCD型号TC253SPD -CCD chip driver VHDL program, CCD models TC253SPD
tPad_Camera
- tPad DE2-115/70开发板可用的摄像头采集、显示程序，QT10.0以上环境可用，原装代码，可以进行修改加以使用，如使用到倒车影像系统中，视频显示等。-tPad DE2-115/70 development board available cameras capture, display program, QT10.0 over the environment is available, the original code can be modified to be used, such
jow_order
- 这是我准备电子设计大赛时，用VHDL写的一个自动打铃系统，很好的学习资料。-This is when I am going to Electronic Design Contest, use VHDL to write an automatic bell playing system, a very good learning materials.
sopc_uart_rt
- sopc的一个应用例程：应用uart部件搭建的一个sopc系统，调试成功了。包含所有源代码-An application of routine sopc: Application uart component erected a sopc system, commissioning a success. Contains all the source code
clk_vhdl
- Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. Using VHDL language.
qpsk
- qpsk调制解调的FPGA实现。QPSK为调制程序，QPSK-two为解调程序。-qpsk modulation and demodulation of the FPGA. QPSK as the modulation process, QPSK-two for the demodulation process.
Hardware_Multiplier
- 用VHDL写的硬件乘法器，以及测试过了，一个时钟周期内完成乘法运算。被乘数、乘数的宽度通过通用属性GENERIC参数改变而轻松改变，硬件除法器也快好了。-Written by VHDL hardware multiplier, and tested, and a clock cycle multiplication. Multiplicand, multiplier width parameter changes through the common property of GENERIC an